HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 124

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.26
3.8.8.27
3.8.8.28
Intel
Datasheet
124
®
5100 Memory Controller Hub Chipset
INTL[7:2,0] - Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between the initialization code and the device driver
dedicated interrupt line. This read only register and is provided for backwards
compatibility
INTP[7:2,0] - Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
appropriate Assert_INTx commands.
BCTRL[7:2] - Bridge Control Register
This register provides extensions to the PEXCMD register that are specific to PCI-to-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express*) as well as some bits that affect the overall behavior of the “virtual” PCI-to-
PCI bridge embedded within the MCH, e.g., VGA compatible address range mapping.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:12
7:0
7:0
Bit
Bit
Bit
11
10
9
RWO
Attr
Attr
Attr
RO
RO
RO
RO
RV
7-2, 0
0
3Ch
7-2, 0
0
3Dh
7-2
0
3Eh
.
Default
Default
Default
00h
01h
0h
0
0
0
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which
input of the interrupt controller this PCI Express* Port is connected to. Not
used in MCH since the PCI Express* port does not have interrupt lines.
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express* port.
01h: Generate INTA
02h: Generate INTB
03h: Generate INTC
04h: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Reserved. (by PCI-SIG)
DTSS: Discard Timer SERR Status
Not applicable to PCI Express*. This bit is hardwired to 0.
DTS: Discard Timer Status
Not applicable to PCI Express*. This bit is hardwired to 0.
SDT: Secondary Discard Timer
Not applicable to PCI Express*. This bit is hardwired to 0.
Intel
®
Description
Description
Description
.
5100 MCH Chipset—Register Description
The MCH does not have a
Order Number: 318378-005US
July 2009