HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 71

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.3.3
Figure 10.
3.4
Table 27.
July 2009
Order Number: 318378-005US
PCI Express* Config Txns
(including ESI)
PCI Express* MMCFG on
FSB
PCI Express* MMCFG
from ESI or PCI Express*
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, the MCH will generate a Type
1 PCI configuration cycle. A[1:0] of the ESI request packet for the Type 1 configuration
cycle will be 01. Bits 31:2 of the CONFIG_ADDRESS register will be translated to the
A[31:2] field of the ESI request packet of the configuration cycle as shown in
“Type 1 Configuration Address to PCI Address Mapping.”
sent over the ESI to ICH9R.
If the cycle is forwarded to the ICH9R via ESI, the ICH9R compares the non-zero Bus
Number with the Secondary Bus Number and Subordinate Bus Number Registers of its
PCI-to-PCI bridges to determine if the configuration cycle is meant for primary PCI bus,
one of the ICH9R’s PCI Express* ports, or a downstream PCI bus.
Type 1 Configuration Address to PCI Address Mapping
Device Mapping
Each component in a Intel
PCI bus address consisting of; Bus Number, Device Number and Function Number.
Device configuration is based on the PCI Type 0 configuration conventions. All PCI
devices within a Intel
All MCH registers in the Intel
All Intel
defined by Bus, Device, Function, Register address. Some registers do not appear in all
portions of this space and some mechanisms do not access all portions of this space. In
general the configuration space is sparsely populated.
Bit Mapping”
appear. Each row defines a different access mechanism, register, interface, or decoder.
Each column defines a different field of the configuration address.
Configuration Address Bit Mapping (Sheet 1 of 2)
CONFIG_ADDRESS
®
Destination
Both
Source
Not permitted to access MCH or DDR2 registers and will be master aborted. Peer-to-peer accesses
targeting valid MMIO space will be forwarded through appropriate decoding.
®
5100 MCH Chipset configuration registers reside in the configuration space
Source/
5100 MCH Chipset
PCI Address
AD[31:0]
defines where the various fields of configuration register addresses
Bus[7:0]
A[27:20]
®
31
31
1
Bus
5100 MCH Chipset must support Type 0 configuration accesses.
30
®
Reserved
0
5100 MCH Chipset-based system is uniquely identified by a
®
Dev[4:0]
A[19:15]
24
5100 MCH Chipset appear on Bus #0.
24
Device
23
23
Bus Number
Number
Bus
Func[2:0]
A[14:12]
Function
16 15
16 15
Device Number
Device
Number
Extended
Reg[3:0]
A[11:8]
[11:8]
Intel
11 10
11 10
Table 27, “Configuration Address
DW Offset
This configuration cycle will be
Function Number
Function Number
®
5100 Memory Controller Hub Chipset
Reg[5:0]
A[7:3]
BE[7:4]
[5:0]
8
8
7
7
Reg. Index
First DW
BE[3:0]
BE[7:0]
Index
Reg.
Byte in
DW
0915061435
Figure 10,
2
2
1
0 1
Datasheet
1
X X
0
0
Type
Fmt,
Type
N/A
71