HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 23

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Introduction—Intel
Table 1.
July 2009
Order Number: 318378-005US
Terminology (Sheet 1 of 6)
Agent
AGTL
aka
Asserted
Atomic operation
Bank
Buffer
Cache Line
CDM
Cfg, Config
Channel
Character
Chipset Core
Coherent
Command
Completion
Core
CRC
Critical Word First
DDR
Deasserted
Deferred
Transaction
®
Terminology
5100 MCH Chipset
A logical device connected to a bus or shared interconnect that can either initiate accesses
or be the target of accesses. Each thread executing within a processor is a unique agent.
Assisted Gunning Transceiver Logic
also known as
Asserted Signal is set to a level that represents logical true. For signals that end with “#”
this means driving a low voltage. For other signals, it is a high voltage.
A series of operations, any one of which cannot be observed to complete unless all are
observed to complete.
DRAM chips are divided into multiple banks internally. Commodity parts are all 4-bank,
which is the only type the MCH supports. Each bank acts somewhat like a separate DRAM,
opening and closing pages independently, allowing different pages to be open in each.
Most commands to a DRAM target a specific bank, but some commands (i.e., Precharge
All) are targeted at all banks. Multiple banks allows higher performance by interleaving
the banks and reducing page miss cycles.
1.
2.
The unit of memory that is copied to and individually tracked in a cache. Specifically, 64
bytes of data or instructions aligned on a 64-byte physical address boundary.
Central Data Manager. A custom array within the Intel
temporary repository for system data in flight between the various ports: FSBs, DIMMs,
ESI, and PCI Express*.
Abbreviation for “Configuration”.
In the MCH a DIMM DRAM channel is the set of signals that connects to one set of DIMMs.
The MCH has up to two DRAM channels.
The raw data byte in an encoded system (e.g., the 8b value in a 8b/10b encoding
scheme). This is the meaningful quantum of information to be transmitted or that is
received across an encoded transmission path.
The MCH internal base logic.
Transactions that ensure that the processor’s view of memory through the cache is
consistent with that obtained through the I/O subsystem.
The distinct phases, cycles, or packets that make up a transaction. Requests and
completions are referred to generically as Commands.
A packet, phase, or cycle used to terminate a transaction on an interface, or within a
component. A Completion will consistently refer to a preceding request and may or may
not include data and/or other information.
The internal base logic in the MCH.
Cyclic Redundancy Check; A number derived from, and stored or transmitted with, a block
of data in order to detect corruption. By recalculating the CRC and comparing it to the
value originally transmitted, the receiver can detect some types of transmission errors.
On the DRAM, Processor, and Memory interfaces, the requestor may specify a particular
word to be delivered first. This is done using address bits of lower significance than those
required to specify the cache line to be accessed. The remaining data is then returned in a
standardized specified order.
Double Data Rate SDRAM. DDR describes the type of DRAMs that transfers two data items
per clock on each pin. This is the only type of DRAM supported by the MCH.
Signal is set to a level that represents logical false.
A processor bus split transaction. On the processor bus, the requesting agent receives a
deferred response which allows other transactions to occur on the bus. Later, the
response agent completes the original request with a separate deferred reply transaction
or by a deferred phase.
A random access memory structure.
The term I/O buffer is also used to describe a low level input receiver and output
driver combination.
Description
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset that acts as a
Datasheet
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