HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 26

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 1.
Intel
Datasheet
26
®
5100 Memory Controller Hub Chipset
Terminology (Sheet 4 of 6)
Page Replace Aka
Page Miss, Row
Hit/Page Miss.
PCI
PCI 2.3 compliant
Peer-to-peer
Phit
Plesiochronous
POC
Posted
Primary PCI
Push Model
Queue
Terminology
An access to a row that has another page open. The page must be transferred back from
the sense amps to the array, and the bank must be precharged.
Peripheral Component Interconnect Local Bus. A 32-bit or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect mechanism
within a system between processor/memory and peripheral components or add-in cards.
Refers to compliance to the PCI Local Bus Specification, Rev. 2.3
Transactions that occur between two devices below the PCI Express* or ESI ports.
The smallest physical unit of information at the physical layer, which is transferred across
the width of one physical link in one cycle.
Each end of a link uses an independent clock reference. Support of this operational mode
places restrictions on the absolute frequency difference, as specified by PCI Express*,
which can be tolerated between the two independent clock references.
Power-On-Configuration settings determined at power-up by strapping pins. Additionally,
the POC Register settings are driven on the address pins when RESET# is issued to the
processor.
A transaction that is considered complete by the initiating agent or source before it
actually completes at the target of the request or destination. All agents or devices
handling the request on behalf of the original Initiator must then treat the transaction as
being system visible from the initiating interface all the way to the final destination.
Commonly refers to memory writes.
The physical PCI bus that is driven directly by the ICH9R component. Communication
between PCI and the MCH occurs over ESI. Note that even though the Primary PCI bus is
referred to as PCI it is not PCI Bus 0 from a configuration standpoint.
Method of messaging or data transfer that predominately uses writes instead of reads.
A storage structure for information. Anything that enters a queue will exit eventually. The
most common policy to select an entry to read from the queue is FIFO (First In First Out).
Description
Intel
®
5100 MCH Chipset—Introduction
Order Number: 318378-005US
July 2009