HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 312

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 95.
Note:
5.13.4
Table 96.
Intel
Datasheet
312
®
5100 Memory Controller Hub Chipset
PCI Express* Link Width Strapping Options for Port CPCI Configuration in
Intel
The PCI Express* Base Specification, Rev. 1.0a requires that a port be capable of
negotiating and operating at the native width and 1x. The Intel
support the following link widths for its PCI Express* ports x16, x8, x4 and x1. During
link training, the MCH will attempt link negotiation starting from its native link width
from the highest and ramp down to the nearest supported link width that passes
negotiation. For example, a port strapped at 8x, will first attempt negotiation at 8x. If
that attempt fails, an attempt is made at x4 and finally a x1 link. Note that the x8 and
x4 link widths will only use the LSB positions from lane 0 while a x1 can be connected
to any of the four positions (lane 0, lane 1, lane 2, lane 3) providing a higher tolerance
to single point lane failures. When settling on a narrower width and the straps are used
to over-ride the auto-negotiation partitioning, the remaining links are unused. The links
will use the LSB wires of the physical layer to route the packets for the negotiated
width.
PCI Express* Port Support Summary
Table 96, “Options and Limitations”
the MCH PCI Express* ports.
Options and Limitations (Sheet 1 of 2)
Number of supported ports
Max payload
PCI Hot Plug*
Virtual Channels
Note:
1.
PEWIDTH[3:0]
®
others
others
0000
0001
0010
0011
0100
1000
1001
1010
1011
1100
1111
Link negotiation configuration is not recommended due to an erratum; see Erratum 1, PCI Express*
auto link negotiation occasionally fails to correctly detect link width in
Hub Chipset Specification Update.
5100 Memory Controller Hub Chipset
Parameter
Port0
(ESI)
x4.
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
The MCH will support six x4 standard PCI Express* ports and an additional
x4 ESI port for ICH9R. (Total: 6+1=7 ports)
256 bytes
The MCH does support PCI Hot Plug*.
The MCH only supports VC0
Port2
x4
x4
x4
x4
x4
describes the options and limitations supported by
x8
x8
x8
x8
x8
All port widths determined by link negotiation.
Port3
x4
x4
x4
x4
x4
Intel
®
Reserved
Reserved
Port4
5100 MCH Chipset—Functional Description
x4
x4
x4
x4
Support
x8
x8
x8
x8
Port5
x4
x4
x4
x4
Intel
®
Order Number: 318378-005US
5100 MCH Chipset will
®
x16
x16
5100 Memory Controller
Port6
x4
x4
x4
x4
1
x8
x8
x8
x8
July 2009
Port7
x4
x4
x4
x4