HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 139

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 55.
3.8.11
3.8.11.1
3.8.11.2
July 2009
Order Number: 318378-005US
IV Handling and Processing by Intel
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them and the MCH will not
PCI Express* Capability Structure
The PCI Express* capability structure describes PCI Express* related functionality,
identification and other information such as control/status associated with the port. It
is located in the PCI 2.3 compatible space and supports legacy operating system by
enabling PCI software transparent features.
PEXCAPL[7:2,0]- PCI Express* Capability List Register
The PCI Express* Capability List register enumerates the PCI Express* Capability
structure in the PCI 2.3 configuration space.
PEXCAP[7:2,0] - PCI Express* Capabilities Register
The PCI Express* Capabilities register identifies the PCI Express* device type and
associated capabilities.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Number of Messages Enabled by Software (MSICTRL.MMEN)
15:14
15:8
7:0
modify any of the “x” bits except the LSB as indicated in
Memory Controller Hub Chipset”
7:0
Bit
Bit
Bit
®
Attr
Attr
Attr
RW
RO
RO
RV
5100 MCH Chipset
7-2, 0
0
60h
7-2, 0
0
6Ch
7-2, 0
0
6Eh
Default
Default
Default
00h
10h
0h
0h
IV: Interrupt Vector
The interrupt vector (LSB) will be modified by the Intel
provide context sensitive interrupt information for different events that require
attention from the processor, e.g., PCI Hot Plug*, Power Management and RAS
error events.
Depending on the number of Messages enabled by the processor in
3.8.10.3, “MSICTRL[7:2,0] - Message Control Register,” Table 55, “IV Handling
and Processing by Intel® 5100 Memory Controller Hub Chipset”
breakdown.
NXTPTR: Next Ptr
This field is set to NULL pointer to terminate the PCI capability list.
CAPID: Capability ID
Provides the PCI Express* capability ID assigned by PCI-SIG.
Reserved.
1
as a function of MMEN
®
5100 Memory Controller Hub Chipset
Table 55, “IV Handling and Processing by Intel® 5100
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Events
All
®
5100 MCH Chipset to
xxxxxxxx
IV[7:0]
illustrates the
Section
Datasheet
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