HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 275

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
Table 86.
4.5
July 2009
Order Number: 318378-005US
Address Disposition for Inbound Transactions (Sheet 2 of 2)
1. One and only one BCTRL can set the VGAEN; otherwise, send to ESI for master abort.
2. Other combinations of PAM’s are not allowed if inbound accesses to this region can occur. Chipset functionality
I/O Address Map
The I/O address map is separate from the memory map and is primarily used to
support legacy code/drivers that use I/O mapped accesses rather than memory
mapped I/O accesses. Except for the special addresses listed in
I/O
PCI Express* port, which will route the I/O access to the appropriate device.
Low MMIO
PCI Express*
MMCFG
Address Range
SMRAM Space
MCH Chipset-
ICH9R/ICH9R
High Memory
Low/Medium
is not guaranteed.
Intel
High MMIO
High SMM
All others
Extended
Firmware
I/O APIC
Interrupt
Addresses”, I/O accesses are decoded by range and sent to the appropriate ESI/
registers
Memory
specific
timers
®
5100
®
5100 MCH Chipset
10_0000 <= Addr < ESMMTOP -
TSEG_SZ
ESMMTOP -TSEG_SZ <= Addr <
ESMMTOP
TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
HECBASE <= Addr <
HECBASE+256 MB
FE00_0000h to FEBF_FFFFh and
valid Intel
memory mapped register address
FE00_0000h to FEBF_FFFFh AND
NOT a valid Intel
Chipset memory mapped register
address
FEC0_0000 to FEC8_FFFFh
FEC9_0000h to FED1_FFFF
FEDA_0000h to FEDB_FFFF
Inbound write to FEE0_0000h -
FEEF_FFFFh
memory transaction (other than
write) to FEE0_0000h -
FEEF_FFFFh
FF00_0000h to FFFF_FFFFh
1_0000_0000 to MIR[x].LIMIT
(depending on the physical
memory external)
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
All Others (subtractive decoding)
®
Conditions
5100 MCH Chipset
®
5100 MCH
Coherent Request to Main Memory. Route to main
memory according to SC.MIR registers. Apply
Coherence Protocol.
Send to system memory if G_SMRAME = 0 or
(G_SMRAME = 1 and T_EN = 0); otherwise Send to
ESI to be master aborted. Set EXSMRAMC.E_SMERR
bit
Request to PCI Express* based on <MBASE/MLIMIT
and PMBASE/PMLIMIT> registers.
Send to ESI to be master aborted.
Inbound MMCFG access is not allowed and will be
aborted.
Inbound MMCFG access is not allowed and will be
aborted.
Send to ESI to be master aborted.
Non-coherent request to PCI Express* or ESI based
on
Issue request to ESI.
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR bit
Route to appropriate FSB(s). See
“Interrupts”
Send to ESI to be master aborted.
Master abort
Coherent Request to Main Memory. Route to main
memory according to SC.MIR registers. Apply
Coherence Protocol.
Route request to appropriate PCI Express* port
Issue request to ESI. There will be a subtractive
agent within ICH, where it will attempt to decode the
address. For undecoded address, transactions will be
aborted. Non-posted transactions will be
acknowledged with unsupported request (UR), and
posted request will be dropped.
Table 80, “I/O APIC Address Mapping”
Intel
Intel
for details on interrupt routing.
®
5100 MCH Chipset Behavior
®
5100 Memory Controller Hub Chipset
Section 4.5.1, “Special
Section 5.3,
Datasheet
275