HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 67

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
expansion bus is physically attached to the ICH9R, and from a configuration
perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge; therefore,
it has a programmable PCI Bus number.
The MCH contains 12 PCI devices within a single physical component. The configuration
registers for these devices are mapped as devices residing on PCI bus 0.
• Device 0: ESI bridge/PCI Express* Port 0. Logically, this appears as a PCI device
• Device 2: PCI Express* 2. Logically this appears as a PCI device residing on bus 0.
• Device 3: PCI Express* 3. Logically this appears as a PCI device that resides on
• Device 4: PCI Express* 4. Logically this appears as a PCI device that resides on
• Device 5: PCI Express* 5. Logically this appears as a PCI device that resides on
• Device 6: PCI Express* 6. Logically this appears as a PCI device residing on bus 0.
• Device 7: PCI Express* 7. Logically this appears as a PCI device residing on bus 0.
• Device 8: DMA Engine Controller. Logically this appears as DMA device residing on
that resides on PCI bus 0. Physically Device 0, Function 0 contains the PCI
Express* configuration registers for the ESI port, and other MCH specific registers.
PCI Express* port 0 resides at DID of 65C0h.
Device 2, Function 0 is routed to the PCI Express* configuration registers for PCI
Express* port 2. When PCI Express* ports 2 and 3 are combined into a single x8
port, controlled by port 2 registers, Device 3, Function 0 (port 3) configuration
registers are inactive. PCI Express* port 2 resides at DID of 65E2h.
bus 0. Device 3, Function 0 contains the PCI Express* configuration registers for
PCI Express* port 3. When PCI Express* ports 2 and 3 are combined into a single
x8 port, controlled by port 2 registers, these configuration registers are inactive.
PCI Express* port 3 resides at DID of 65E3h.
bus 0. Device 4, Function 0 contains the PCI Express* configuration registers for
PCI Express* port 4. When PCI Express* ports 4 and 5 are combined into a single
x8 port, Device 4, Function 0 contains the configuration registers and Device 5,
Function 0 (port 5) configuration registers are inactive. When PCI Express* ports 4,
5, 6, and 7 are combined into a single x16 graphics port, Device 4, Function 0
contains the configuration registers and Device 5, Function 0 (port 5), Device 6,
Function 0 (port 6), and Device 7, Function 0 (port 7), configuration registers are
inactive. PCI Express* port 4 resides at DID of 65E4h.
bus 0. Device 5, Function 0 contains the PCI Express* configuration registers for
PCI Express* port 5. When PCI Express* ports 4 and 5 are combined into a single
x8 port Device 4, Function 0 contains the configuration registers, and these
configuration registers are inactive. When PCI Express* ports 4, 5, 6 and 7 are
combined into a single x16 graphics port Device 4, Function 0 contains the
configuration registers, and these configuration registers are inactive. PCI Express*
port 5 resides at DID of 65E5h.
Device 6, Function 0 contains the PCI Express* configuration registers for PCI
Express* port 6. When PCI Express* ports 6 and 7 are combined into a single x8
port Device 6, Function 0 contains the configuration registers, and Device 7,
Function 0 (port 7) configuration registers are inactive. When PCI Express* ports 4,
5, 6 and 7 are combined into a single x16 graphics port Device 4, Function 0
contains the configuration registers, and these configuration registers are inactive.
PCI Express* port 6 resides at DID of 65E6h.
Device 7, Function 0 contains the PCI Express* configuration registers for PCI
Express* port 7. When PCI Express* ports 6 and 7 are combined into a single x8
port Device 6, Function 0 contains the configuration registers, and these
configuration registers are inactive. When PCI Express* ports 4, 5, 6 and 7 are
combined into a single x16 graphics port Device 4, Function 0 contains the
configuration registers, and these configuration registers are inactive. PCI Express*
port 2 resides at DID of 65E7h.
bus 0. Device 8, Function 0 contains the DMA controller configuration registers for
®
5100 MCH Chipset
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
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