HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 240

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.22
Table 76.
3.11.22.1
Intel
Datasheet
240
®
5100 Memory Controller Hub Chipset
DMA Registers
Table 76
functionality. The DMA channel specific information is contained in four locations
starting from offset 80h of the CB_BAR register. Each channel is separated by 128
bytes from other channels. For software compatibility, the DMA Engine device is
required to implement these registers at the listed memory-mapped offsets.
There is one set of general registers followed by multiple sets of per-channel registers
(i.e., one set for each of the 4 DMA channels of the MCH).
All of these registers are accessible from both a processor and an I/O device from the
PCI Express* ports 2 and 3.
DMA Memory Mapped Register Set Locations
CHANCNT - Channel Count
The Channel Count register specifies the number of channels that are implemented.
Device:
Function:
Offset:
2
1
0
Offset:
7:5
4:0
Bit
Bit
RWCST
RWCST
RWCST
RV
RO
Attr
lists the memory-mapped registers used to control the chipset DMA
Attr
8
0
BCh
00h
General Registers
Register Set
0h
00100
Default
Channel 0
Channel 1
Channel 2
Channel 3
0
0
0
Default
Reserved
num_chan: Number of channels
Specifies the number of DMA channels. The Intel
DMA Channels.
Note:
NERR_Next Descriptor_ Address_Error_DMA2
The DMA channel sets this bit indicating that the current descriptor has an
illegal next descriptor address (e.g., > 40-bits) including next descriptor
alignment error (not on a 64-byte boundary). This error could be flagged when
the data for the current descriptor is fetched and its constituent fields are
checked.
NERR_DMA Transfer_Destination_Address_Error_DMA1
The DMA channel sets this bit indicating that the current descriptor has an
illegal destination address.
NERR_DMA Transfer_Source Address_Error_DMA0
The DMA channel sets this bit indicating that the current descriptor has an
illegal source address.
This field will be set to “00000” by the chipset when the DMA Engine is
disabled. Refer to
Offset from CB_BAR
0000h
0080h
0100h
0180h
0200h
Section 3.11.8
Intel
Description
Description
®
5100 MCH Chipset—Register Description
for details.
®
5100 MCH Chipset supports four
Order Number: 318378-005US
July 2009