HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 280

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.2
5.2.1
5.2.2
Intel
Datasheet
280
®
5100 Memory Controller Hub Chipset
System Memory Controller
The Intel
can be connected to each DDR2 channel (up to six DIMMs for the entire array)
supporting up to 16 GB per channel for a total of 32 GB of memory space for
32GB_Mode or supporting up to 24 GB per channel for a total of 48 GB of memory
space for 48GB_Mode.
The key features of the DDR memory interface are summarized in the following list.
Memory Size
The minimum configuration is a single channel populated with 256 MB: one channel
containing one DIMM with 256 MB of DDR2 devices (nine 32Mx8 devices). The MCH can
support up to 48 GB of physical memory using the largest system memory
configuration supported by 2 Gb DRAM devices. The maximum configuration allows 36-
bit address space with 48 GB of accessible memory. Both channels support up to six
memory ranks for a total of 48 GB installed system memory.
DIMM Technology and Organization
The Intel
per channel. The Intel
“Representative Memory System 32 GB Mode.”
DIMM configurations are highly recommended for proper operation of the interface. The
Intel
three single rank, up to three double (dual) rank, or up to one quad rank DDR2
Registered DIMM(s). For currently supported DIMM configurations, see the Quad-Core
and Dual-Core Intel
Controller Hub Chipset for Communications, Embedded, and Storage Applications –
Platform Design Guide or Intel
5100 Memory Controller Hub Chipset for Communications and Embedded Applications
– Platform Design Guide.
• Two independent DDR2 Channels
• Supports DDR2-533 and DDR2-667 technology
• Minimum configuration 256 MB/single channel; 512 MB for two channels
• Maximum capacity 24 GB for single channel, 48 GB for two channels
• Supports 256 Mb to 2 Gb devices
• Supports x4 and x8 devices (RDQS mode for x8 devices)
• All writes are full cache line, data mask not supported
• Supports only Registered ECC DIMMs
• Supports up to six ranks/channel
• Intelligent Page-Hit policy
• Supports DIMM Self-refresh mode for low power (S3) mode
• Supports ECC and SDDC (x4 only)
• Address glitch detection built into ECC Algorithm
• Rank sparing capability on each channel
• Patrol and background scrubbing
®
5100 MCH Chipset, in 48 GB Mode, supports up to six ranks per channel, up to
®
®
5100 MCH Chipset provides two DDR2 memory channels. Up to three DIMMs
5100 MCH Chipset in standard 32 GB operation, supports up to four ranks
®
®
Xeon
5100 MCH Chipset’s DIMM organization is shown in
®
Processor 5000 Sequence with Intel
®
Core™2 Duo Processors T9400 and SL9400 and Intel
Intel
Signal integrity simulations for the
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
®
5100 Memory
Figure 18,
July 2009
®