HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 358

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Figure 48.
Figure 49.
Figure 50.
5.20.5.4
5.20.5.5
Intel
Datasheet
358
®
5100 Memory Controller Hub Chipset
SMBus Configuration Write (Block Write, PEC Enabled)
SMBus Configuration Write (Word Writes, PEC Enabled)
SMBus Configuration Write (Write Bytes, PEC Enabled)
SMBus Error Handling
The SMBus slave interface handles two types of errors: Internal and PEC. For example,
internal errors can occur when the Intel
on the PCI Express* port that read’s terminates in error. These errors manifest as a
not-acknowledge (NAK) for the read command (End bit is set). If an internal error
occurs during a configuration write, the final write command receives a NAK just before
the stop bit. If the master receives a NAK, the entire configuration transaction should
be reattempted.
If the master supports Packet Error Checking (PEC) and the PEC_en bit in the command
is set, then the PEC byte is checked in the slave interface. If the check indicates a
failure, then the slave will NAK the PEC packet.
SMBus Interface Reset
S
• The slave interface state machine can be reset by the master in two ways:
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
• The master holds SCL continuously high for 50 ms.
S
S
S
S
S
S
S
S
S
S
S
S
11X0_XXX
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
1 1 X 0_ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
1 1X 0 _ X X X
W A
Cmd = 11011110
W A
W A
W A
W A
W
W
W
W
W
W
W
W
Cmd = 10011101
Cmd = 00011101
Cmd = 00011101
Cmd = 01011101
A
A
A
A
A
A
A
A
A
Byte Count = 8
Cm d = 0 0 0 11 1 0 0
Cm d = 1 00 1 1 1 00
Cm d = 0 00 1 1 1 00
Cm d = 0 00 1 1 1 00
Cm d = 0 00 1 1 1 00
Cm d = 0 00 1 1 1 00
Cm d = 0 00 1 1 1 00
Cm d = 0 10 1 1 1 00
A
A
A
A
A
A
Bus Number
Data[23:16]
Register[15:8]
Bus Number
Data[31:24]
Data[15:8]
®
5100 MCH Chipset issues a configuration read
A
A
A
A
A
A
A
A
A
A
Intel
Device/Function
Device/Fu nct io n
R egist er[15 :8 ]
Data[16:8]
Register[7 :0 ]
B u s N um ber
Da ta[3 1 :2 4 ]
Da ta[2 3 :1 6 ]
A
A
A
A
Da ta[1 5 :8 ]
®
Dat a[7 :0 ]
5100 MCH Chipset—Functional Description
Device/Function
Register[7:0]
Data[23:16]
A
Data[7:0]
A
Reg Number[15:8]
Data[7:0]
A
A
A
A
A
A
A
A
Order Number: 318378-005US
A
A
A
A
A
A
Reg Number [7:0]
PEC
PEC
PEC
P EC
PEC
PEC
PEC
PEC
PEC
PEC
PEC
PEC
PEC
A
CLOCK STRETCH
Data[31:24]
A P
A P
A P
A P
July 2009
A
A
A
A
A
A
A
A
P
P
P
P
P
P
P
P
A P