HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 236

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.21.3
Intel
Datasheet
236
®
5100 Memory Controller Hub Chipset
1. An illegal address is one which is flagged by the Intel
FERR_CHANCMD - First Error Channel Command Register
This register records the first error of the CHANCMD register when the unaffiliated error
happens (i.e., more than 1 bit is set in this register)
Device:
Function:
Offset:
4
3
2
1
0
Device:
Function:
Offset:
7:5
4
3
2
1
0
Bit
Bit
(e.g., hitting a reserved space in memory) or which is decoded by the DMA Engine as erroneous, e.g., >40-
bits in length or an alignment issue.
RWCST
RWCST
RWCST
RWCST
RWCST
RV
RWCST
RWCST
RWCST
RWCST
RWCST
Attr
Attr
8
0
80h
8
0
83h
0
0
0
0
0
Default
0h
0
0
0
0
0
Default
FERR_Chain Address_Value_Error_DMA4: FERR_Chain
Address_Value_Error_DMA4
The DMA channel sets this bit indicating that the CHAINADDR register has an
illegal address including an alignment error (not on a 64-byte boundary). This
address will be checked and set by the DMA Engine during execution, i.e., when
the initial descriptor is fetched
FERR_Descriptor_Error_DMA3: FERR_Descriptor_Error_DMA3
The DMA channel sets this bit indicating that the current descriptor has
encountered an error when executing a DMA descriptor that is not otherwise
related to other error bits, e.g., an illegal next descriptor address flagged by the
system Address decoder, which the DMA Engine encounters in the current
descriptor after having successfully completed the data transfer for the current
descriptor including any associated completions/interrupts.
FERR_Next Descriptor_ Address_Error_DMA2: FERR_Next Descriptor_
Address_Error_DMA2
The DMA channel sets this bit indicating that the current descriptor has an illegal
next descriptor address (e.g., > 40-bits) including next descriptor alignment error
(not on a 64-byte boundary). This error could be flagged when the data for the
current descriptor is fetched and its constituent fields are checked.
FERR_DMA Transfer_Destination_Address_Error_DMA1: FERR_DMA
Transfer_Destination_Address_Error_DMA1
The DMA channel sets this bit indicating that the current descriptor has an illegal
destination address.
FERR_DMA Transfer_Source Address_Error_DMA0: FERR_DMA
Transfer_Source Address_Error_DMA0
The DMA channel sets this bit indicating that the current descriptor has an illegal
source address.
Reserved
FERR_Resume DMA: FERR_Resume DMA
Records the “Resume_DMA” field during the occurrence of the first error
FERR_Abort DMA: FERR_Abort DMA
Records the “Abort_DMA” field during the occurrence of the first error
FERR_Suspend DMA: FERR_Suspend DMA
Records the “Suspend_DMA” field during the occurrence of the first error
FERR_Append DMA: FERR_Append DMA
Records the “Append_DMA” field during the occurrence of the first error
FERR_Start DMA: Records the “Start_DMA” field during the occurrence of the
first error
®
5100 MCH Chipset system address decoder as invalid
Intel
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009