HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 296

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.5
5.5.1
5.5.2
Intel
Datasheet
296
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5100 Memory Controller Hub Chipset
I/O Interrupts
For I/O interrupts from the ICH9R components receive interrupts with either dedicated
interrupt pins or with writes to the integrated redirection table. The I/OxAPIC controller
integrated within these components turns these interrupts into writes destined for the
processor bus with a specific address.
Interrupts triggered from an I/O device can be triggered with either a dedicated
interrupt pin or through an inbound write message from the PCI Express* bus (MSI).
Note that if the interrupt is triggered by a dedicated pin, the I/OxAPIC controller in the
I/O bridge (Intel
On the processor bus, the interrupt is converted to an interrupt request. Other than a
special interrupt encoding, the processor bus interrupt follows the same format as
discussed in
components other than the Intel
an interrupt is an inbound write following the format mentioned in
“XAPIC Interrupt Message
combine or cache the APIC address space.
I/O(x)APIC’s can be configured through two mechanisms. The traditional mechanism is
the hard coded FEC0_0000h to FECF_FFFFh range is used to communicate with the
IOAPIC controllers in the Intel
The second method is to use the standard MMIO range to communicate to the Intel
6700PXH 64-bit PCI Hub. To accomplish this, the Intel
and/or Intel
programmed within the PCI Express* device MMIO region.
Ordering
Handling interrupts as inbound writes has inherent advantages. First, there is no need
for the additional APIC bus resulting in extra pins and board routing concerns. Second,
with an out-of-band APIC bus, there are ordering concerns. Any interrupt needs to be
ordered correctly and all prior inbound writes must get flushed ahead of the interrupt.
The PCI Local Bus Specification, Rev. 2.3 attempts to address this by requiring all
interrupt routines to first read the PCI interrupt register. Since PCI read completions
are required to push all writes ahead of it, then all writes prior to the interrupt are
guaranteed to be flushed. However, this assumes that all drivers perform this read.
Hardware IRQ IOxAPIC Interrupts
Dedicated pin interrupts may be edge or level triggered. They are routed to IRQ pins on
IOxAPIC device such as the Intel
device will convert the interrupt into either an XAPIC or 8259 interrupt.
For level-triggered interrupts, the I/OxAPIC will generate an interrupt message when
any of the interrupt lines coming into it become asserted. The processor will handle the
interrupt and eventually write to the initiating device that the interrupt is complete. The
device will deassert the interrupt line to the I/OxAPIC. After the interrupt has been
serviced, the processor sends an EOI command to inform the I/OxAPIC that the
interrupt has been serviced. Since the EOI is not directed, the Intel
will broadcast the EOI transaction to all I/O(x)APIC’s. If the original I/O(x)APIC sees
the interrupt is still asserted, it knows there’s another interrupt (shared interrupts) and
will send another interrupt message.
For edge-triggered interrupts, the flow is the same except that there is no EOI message
indicating that the interrupt is complete. Since the interrupt is issued whenever an
edge is detected, EOIs are not necessary.
®
Section 5.4.1, “XAPIC Interrupt Message
6700PXH 64-bit PCI Hub.XAPIC_BASE_ADDRESS_REG must be
®
6700PXH 64-bit PCI Hub or ICH9R) turns this into an inbound write.
Format”. The Intel
®
6700PXH 64-bit PCI Hub or ICH9R.
®
®
6700PXH 64-bit PCI Hub, ICH9R, and the processor,
6700PXH 64-bit PCI Hub or ICH9R. The IOxAPIC
Intel
®
5100 MCH Chipset will not write
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5100 MCH Chipset—Functional Description
®
Format”. Therefore, to all
6700PXH 64-bit PCI Hub.MBAR
Order Number: 318378-005US
®
Section 5.4.1,
5100 MCH Chipset
July 2009
®