HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 197

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.9.4.2
3.9.4.3
July 2009
Order Number: 318378-005US
DRTB[1:0]: DDR Timing Register B
This register defines timing parameters that work with all DDR ports in the appropriate
channel. This register must be set to provide timings that satisfy the specifications of
all detected DDR ports. For example, if DDR ports have different T
be used to program this register.
DRPADCTL[1:0]: DRAM Pads Control Register
Device:
Function:
Offset:
Device:
Function:
Offset:
31:14
13:11
31:24
22:20
19:14
13:11
10:8
7:4
3:2
1:0
7:4
3:0
Bit
Bit
23
10
9
8
Attr
Attr
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RV
RV
RV
®
5100 MCH Chipset
22, 21
0
150h
22, 21
0
148h
Default
Default
0010
04h
00h
11h
5h
0h
01
01
0h
0h
0h
0h
0
1
0
0
Reserved
FAR: The logical far rank number
NEAR: The logical far rank number
Reserved
T
Measured in mclk cycles. Our RAS->CAS spacing will be 3 cycles for all DRAMs.
T
This parameter depends on the type of memory installed - measured in mclk
cycles:
00: 3 cycles
01: 4 cycles
10: 5 cycles
11: 6 cycles
SLEWOVERRIDE: Slew Rate Override
RANK45DIS: Allows Chip Select / CKE / ODT disables for ranks 4&5.
Used in 6 rank mode only - has no effect in 4 rank mode.
CLOCKCNTL: Clock Control
Coarse delay of CMD/ADD output clock master DLL
LEGOVERRIDE: Leg Over Ride
Drive override for all DDR drivers
Reserved
DQSx4MODE: DQS x4 Mode
Enables DQSx4 Mode for x8 DIMMs
CMDDIS: Command Disable
Disables CMD (RAS/CAS/WE) and ADD signals (save power if channel is not in use.
ADHIDIS: Address High Disable
Disables AD[15:14] and BA[2] pins (‘1’ disables). For smaller 4 bank devices.
CKDIS: Clock disable
Clock disable for DIMMs 3-0 (‘1’ disables). For 2 DIMM solution, to save power, this
value should be written as Ch.
RANKDIS: Chip Select/CKE/ODT disables for ranks 3-0 (‘1’ disables)
AL
CL
: CAS Latency
: Additive Latency
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
R2W
s, the max should
Datasheet
197