HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 374

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 123.
Intel
Datasheet
374
IO18
IO19
MCH Internal Errors
B1
B3
B4
B5
B8
Memory Subsystem
M1
M4
Notes:
1.
2.
ERR #
MCH
in
®
5100 Memory Controller Hub Chipset
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
ESI reset
timeout
Surprise Link
Down
MCH - Parity
Error from DM
(Do not Include
Poisoned Data)
MCH -
Coherency
Violation EWB
Error
Virtual Pin
Interface Error
MCH - Address
Map Error
MCH Coherency
Violation BIL
Error
Uncorrectable
Data ECC Error
on DDR Replay
Aliased
Uncorrectable
Demand Data
ECC Error
Error Name
Intel
2
®
5100 Memory Controller Hub Chipset Error List (Sheet 6 of 7)
Did not receive ESI
CPU_Reset_Done_Ack or
CPU_Reset_Done_Ack_Sec
rets messages within
T
processor RESET# while
PWRGOOD was asserted
IOU LTSSM detected a link
down condition (surprise)
during normal operation
MCH detected internal DM
parity error. (This error
was not generated by
receiving bad data from an
external interface)
MCH detected a cache
coherency protocol error
for EWB.
MCH detected an error on
the virtual pin interface
MCH detected address
mapping error due to
software programming
error. The errors are
described in system
address map section
MCH detected a cache
coherency protocol error
for a BIL.
Any requestor from the
bus that issued BIL not
present in the SF.
The MCH detected an
uncorrectable data ECC
error during replay of the
head of the DDR replay
queue
The MCH determined that
a normally “correctable”
error could be an aliased
(x4 only) full device failure
plus an additional single
bit error.
10max
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
after assertion of
Definition
Non
Fatal
Uncorr
UnCorr
Error
Type
Fatal
Fatal
Fatal
Fatal
Fatal
Rec
NRECMEMA and NRECMEMB
VALIDLOG[1:0], RECMEMA
respective Error types and
Log PEX_FAT_FERR/NERR
Log PEX_FAT_FERR/NERR
or PEX_NF_COR_FERR/
Severity (UNCERRSEV)
NERR based on their
NERR_FAT_INT and
NERR_FAT_INT and
NERR_FAT_INT and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_INT and
NERR_NF_INT and
Intel
VALIDLOG[1:0],
FERR_FAT_INT/
FERR_FAT_INT/
FERR_FAT_INT/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_INT/
FERR_NF_INT/
and RECMEMB
Log Register
NRECINT
NRECINT
NRECINT
NRECINT
NRECINT
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
Deassert processor RESET#.
Necessary to prevent
processor thermal runaway.
Link went down suddenly
and status bits are set for
software to take any action.
log DM Entry on FERR.
Log CE entry on FERR This
applies to SF enable mode
and is not applicable for the
Intel
Log VPP error in the
respective PEX and DDR
Channel cluster debug
registers
MCH might malfunction.
Log CE entry on FERR. This
applies to SF enable mode
and is not applicable for the
Intel
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
Figure 54, “DDR Error
Figure 54, “DDR Error
®
®
376.
376.
Cause/Actions
5100 MCH Chipset.
5100 MCH Chipset.
July 2009