HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 148

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 57.
Intel
Datasheet
148
®
5100 Memory Controller Hub Chipset
1. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel
Negotiated Link Width For Different PCI Express* Ports After Training
1. Ports 3, 5, and 7 report 000000 as appropriate.
2. Ports 5, 6, and 7 report 000000 as appropriate.
Device:
Function:
Offset:
0, 2, 3, 4, 5, 6, 7
9:4
3:0
Note that this field is a don’t care until training is completed for the link. Software should not use this field to
determine whether a link is up (enabled) or not.
Bit
2, 3, 4, 5, 6, 7
2, 3, 4, 5, 6, 7
12
11
10
Device/Port
2, 4, 6
4
RWO
Attr
RO
RO
RO
RO
7-2, 0
0
7Eh
Default
000100
1h
0
0
1
Negotiated Link Width
SCCON: Slot Clock Configuration
This bit indicates that the component uses the same physical reference clock
that the platform provides on the connector. If the device uses an independent
clock irrespective of the presence of a reference on the connector, this bit
must be clear.
1: indicates same physical clock in the PCI Express* connector as in the
platform
0: indicates independent clock on the PCI Express* connector from that of the
platform.
The Intel
state of the platform is to have one clock source shared between the Intel
5100 MCH Chipset component and any down-devices or slot connectors. It is
the responsibility of BIOS to be aware of the real platform configuration, and
clear this bit if the reference clocks differ.
LNKTRG: Link Training
This field indicates the status of an ongoing link training session in the current
PCI Express* port and is controlled by the Hardware.
0: indicates that the LTSSM is neither in “Configuration” nor “Recovery” states.
1: indicates Link training in progress (Physical Layer LTSSM is in Configuration
or Recovery state or the RLNK (retrain link) was set in
“PEXLNKCTRL[7:2,0] - PCI Express* Link Control Register”
not yet begun.
Also refer to the BCTRL.SBUSRESET for details on how the Link training bit can
be used for sensing Hot-Reset states.
TERR: Training Error
This field indicates the occurrence of a Link training error.
0: indicates no Link training error occurred.
1: indicates Link training error occurred.
NLNKWD: Negotiated Link Width
This field indicates the negotiated width of the given PCI Express* link after
training is completed.
Only x1, x2, x4, x8, and x16 link width negotiations are possible in the Intel
5100 MCH Chipset. Refer to
Express* Ports After Training”
training is completed.
LNKSPD: Link Speed
This field indicates the negotiated Link speed of the given PCI Express* Link:
0001- 2.5 Gb/s PCI Express* link
Others - Reserved
x16
x1
x2
x4
x8
®
5100 MCH Chipset initializes this bit to ‘1’ because the expected
Intel
Table 57, “Negotiated Link Width For Different PCI
for the port and link width assignment after
®
001000
010000
000001
000010
000100
Description
Value
5100 MCH Chipset—Register Description
1
1
2
Order Number: 318378-005US
Section 3.8.11.7,
®
but training has
5100 MCH Chipset.
July 2009
®
®