HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 162

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.8
3.8.12.9
3.8.12.10
Intel
Datasheet
162
®
5100 Memory Controller Hub Chipset
CORERRSTS[7:2,0] - Correctable Error Status
This register identifies which unmasked correctable error has been detected. The error
is directed to the respective device correctable error bit in the PEX_NF_COR_FERR,
PEX_NF_COR_NERR registers (If the error is unmasked in the CORERRMSK register
defined in
registers are discussed starting from
PCI Express* First Non-Fatal or Correctable Error Register.”
CORERRMSK[7:2,0] - Correctable Error Mask
This register masks correctable errors from being signaled. They are still logged in the
CORERRSTS register.
AERRCAPCTRL[7:2,0] - Advanced Error Capabilities and Control
Register
This register identifies the capability structure and points to the next structure.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:13
31:13
11:9
11:9
5:1
5:1
Bit
Bit
12
12
8
7
6
0
8
7
6
0
RWCST
RWCST
RWCST
RWCST
RWCST
RWST
RWST
RWST
RWST
RWST
Attr
Section 3.8.12.9, “CORERRMSK[7:2,0] - Correctable Error
Attr
RV
RV
RV
RV
RV
RV
7-2, 0
0
110h
7-2, 0
0
114h
Default
Default
0h
0h
0h
0
0
0
0
0
0h
0h
0h
0
0
0
0
0
Reserved
IO16Err: Replay Timer Timeout Status
Reserved
IO15Err: Replay_Num Rollover Status
IO14Err: Bad DLLP Status
IO13Err: Bad TLP Status
Reserved
IO12Err: Receiver Error Status
Reserved
IO16Msk: Replay Timer Timeout Mask
Reserved
IO15Msk: Replay_Num Rollover Mask
IO14Msk: Bad DLLP Mask
IO13Msk: Bad TLP Mask
Reserved
IO12Msk: Receiver Error Mask
Section 3.8.12.25, “PEX_NF_COR_FERR[7:2,0] -
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Order Number: 318378-005US
Mask”). These
July 2009