HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 284

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.2.4.5
5.2.4.6
5.2.4.7
Intel
Datasheet
284
®
5100 Memory Controller Hub Chipset
Normal Correction
This correction mode is in effect when the MC.SCRBALGO configuration bit is cleared.
An erroneous read will be logged. If the ECC was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request pending issue will be held until the scrub
is completed.
Enhanced Correction
This correction mode is in effect when the MC.SCRBALGO configuration bit is set and
software has initialized the MC.BADRAMTH to a non-zero value.
Upon incrementing BADCNT to saturation, then it marks the bad devices in the
BADRAM(A/B) configuration registers.
An erroneous read will be logged. If the read was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request remains pending until the scrub
succeeds or is dropped. A failed scrub is replayed once, resulting in success or a drop.
Single Device Data Correction (SDDC) Support
The Intel
algorithm for the memory subsystem that will recover from a x4 component failure.
The algorithm does not recover from a x8 component failure. The chip disable is a 32-
byte two-phase code. In addition, the MCH supports demand and patrol scrubbing.
A scrub corrects a correctable error in memory. A four-byte ECC is attached to each 32-
byte “payload”. An error is detected when the ECC calculated from the payload
mismatches the ECC read from memory. The error is corrected by modifying either the
ECC or the payload or both and writing both the ECC and payload back to memory.
Only one demand or patrol scrub can be in process at a time.
The attributes of the SDDC code are as follows:
• Maintain 4-bit saturating counters per rank in the BADCNT configuration registers:
• Maintain five-bit bad-device marks per rank in the BADRAM(A/B) configuration
• A correctable ECC in a symbol other than that marked in the BADRAM(A/B)
• Two Phase Code over 32 bytes of data.
• 100% Correction for all single x4 component failures.
• 100% Detection of all double x4 component failures.
floor value at zero, saturation at the value of the MC.BADRAMTH configuration
register field, increment on correctable errors, decrement upon completion of the
number of patrol scrub cycles through the entire memory specified by the
MC.BADRAMTH configuration register field -- a sufficient resolution of this period is
three patrol scrub cycles through all memory.
registers.
configuration registers is an aliased uncorrectable read.
— double bit errors
— double wire faults
— single wire fault in addition to single bit error
— single x4 device error in addition to single bit error
— single x4 device error in addition to single wire fault
— double x4 device error
®
5100 MCH Chipset employs a single device data correction (SDDC)
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
July 2009