HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 292

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.4.1
Figure 20.
Table 92.
5.4.2
5.4.2.1
Intel
Datasheet
292
®
5100 Memory Controller Hub Chipset
both I/O interrupts and IPIs. The redirection can be performed in logical and physical
destination modes. For more details on the interrupt redirection algorithm, see
5.4.3, “Interrupt
XAPIC Interrupt Message Format
Interrupt messages have an address of 000_FEEz_zzzYh. The 16-bit “zzzz” field
(destination field) determines the target to which the interrupt is being sent. The Y field
is mapped to A[3] (redirectable interrupt) and A[2] (destination mode).
“XAPIC Address Encoding”
each interrupt there is only one data transfer. The data associated with the interrupt
message specifies the interrupt vector, destination mode, delivery status, and trigger
mode. The transaction type on the processor bus is a request type of, interrupt
transaction. The transaction type on the PCI Express* and ESI buses is a write. The
address definition of
Express* bus and processor bus. Note that the current assumption is that no
conclusions can be made about which FSB an interrupt ID is associated with. At power-
up, there is an association for certain types of interrupts, but the current assumption is
that the OS can reprogram the interrupt ID’s. Therefore, for directed interrupts, the
Intel
XAPIC Address Encoding
The data fields of an interrupt transaction are defined by the processor and XAPIC
specifications. It is included here for reference.
XAPIC Data Encoding
XAPIC Destination Modes
The destination mode refers to how the processor interprets the destination field of the
interrupt message. There are two types of destination modes; physical destination
mode, and logical destination mode. The destination mode is selected by A[2] in PCI
Express* and FSBxAb[5]# on the processor bus.
Physical Destination Mode (XAPIC)
In physical mode, the APIC ID is eight bits, supporting up to 255 agents. Each
processor has a Local APIC ID Register where the lower five bits are initialized by
hardware (Cluster ID=ID[4:3], Bus Agent ID=ID[2:1], thread ID=ID[0]). The upper
three bits default to 0’s at system reset. These values can be modified by software. The
Cluster ID is set by address bits FSBxA[12:11]# during reset. By default, the Intel
5100 MCH Chipset will drive FSBxA[12:11]# to ‘00 for FSB0, and ‘01 for FSB1. The
value driven on bit FSBxA[12]# during reset can be modified through the
3.8.5.3, “POC - Power-On Configuration Register”
DID: 8-bit destination ID. Software may assign each ID to any value. (A[19:12])
EDID: Not used, is a reserved field in the Processor EHS.
rh: redirection hint bit, 0=directed, 1=redirectable (A[3])
dm: destination mode, 0=physical, 1=logical (A[2])
† PCI/PCI Express* transaction encoding. Copied to FSBxAb[5]# on processor bus
31
D[63:16]
®
FEEh
x
5100 MCH Chipset will ensure that each interrupt is seen on both FSBs.
Trigger Mode
Redirection”.
D[15]
Figure 20, “XAPIC Address Encoding”
20 19
shows the address definition in IA-32 systems (XAPIC). For
Delivery Status
DID
D[14]
Intel
12 11
D[13:11]
®
EDID (not used)
on the Intel
5100 MCH Chipset—Functional Description
x
applies to both the PCI
Delivery Mode
®
D[10:8]
Order Number: 318378-005US
5100 MCH Chipset.
4
rh dm rsvd
3
2†
Figure 20,
Section
D[7:0]
Vector
0
Section
July 2009
®