HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 259

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
4.1.1
July 2009
Order Number: 318378-005US
32/64-bit Addressing
For inbound and outbound writes and reads, the Intel
bit address format. If an outbound transaction’s address is a 32-bit address, the Intel
5100 MCH Chipset will issue the transaction with a 32-bit addressing format on PCI
Express*. Only when the address requires more than 32 bits will the Intel
Chipset initiate transactions with 64-bit address format. It is the responsibility of the
software to ensure that the relevant bits are programmed for 64-bits based on the OS
limits. The Intel
interfaces. If configuration registers for these interfaces expose extra address bits, the
BIOS should initialize the most-significant bits to zero because UP/DP processors only
support 36-bit addressing.
®
5100 MCH Chipset
®
5100 MCH Chipset implements 40-bit addressing on some internal
Intel
®
5100 MCH Chipset supports 64-
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
259
®