HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 49

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 10.
2.3.3
Table 11.
2.3.4
Table 12.
July 2009
Order Number: 318378-005US
PCI Express* Port 0, Enterprise South Bridge Interface (ESI) Signals
PCI Express* Port 2
PCI Express* port 2 is a x4 port. PCI Express* port 2 can be combined with PCI
Express* port 3 to form a single PCI Express* x8 port. The combined x8 PCI Express*
port is controlled by the configuration registers of the lowest x4 port number, the other
port registers are inactive.
PCI Express* Port 2 Signals
PCI Express* Port 3
PCI Express* port 3 is a x4 port. PCI Express* port 3 is combinable with PCI Express*
port 2 to form a single PCI Express* x8 port. The combined x8 PCI Express* port is
controlled by the configuration registers of the lowest x4 port number, the other port
registers are inactive.
PCI Express* Port 3 Signals
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
Signal Name
Signal Name
Signal Name
®
5100 MCH Chipset
Type
Type
Type
O
O
O
O
O
O
I
I
I
I
I
I
PCI Express* Port 0 (ESI) Positive Phase Inbound:
(Receive) Signals
PCI Express* Port 0 (ESI) Negative Phase Inbound:
(Receive) Signals
PCI Express* Port 0 (ESI) Positive Phase Outbound:
(Transmit) Signals
PCI Express* Port 0 (ESI) Negative Phase Outbound:
(Transmit) Signals
PCI Express* Port 2 Positive Phase Inbound:
(Receive) Signals
PCI Express* Port 2 Negative Phase Inbound:
(Receive) Signals
PCI Express* Port 2 Positive Phase Outbound:
(Transmit) Signals
PCI Express* Port 2 Negative Phase Outbound:
(Transmit) Signals
PCI Express* Port 3 Positive Phase Inbound:
(Receive) Signals
PCI Express* Port 3 Negative Phase Inbound:
(Receive) Signals
PCI Express* Port 3 Positive Phase Outbound:
(Transmit) Signals
PCI Express* Port 3 Negative Phase Outbound:
(Transmit) Signals
Description Reference
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
49