HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 272

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 82.
4.4.2.1
Table 83.
Intel
Datasheet
272
®
5100 Memory Controller Hub Chipset
Address Disposition for Processor (Sheet 2 of 2)
Access to SMM Space (Processor Only)
Accesses to SMM space are restricted to processors, inbound transactions are
prohibited. Inbound transactions to enabled SMM space are not allowed and the Intel
5100 MCH Chipset will set SC.EXSMRAMC.E_SMERR bit.
Ranges”
H_SMRAM_EN, and TSEG_EN are located in the SC.EXSMRC register.
Enabled SMM Ranges
The processor bus has a SMMEM# signal that qualifies the request asserted as having
access to a system management memory. The SMM register defines SMM space that
may fall in one of three ranges: legacy SMRAM, Extended SMRAM Space (TSEG), or
High SMRAM Space (H_SMM).
Processor”
High SMM
Interrupt
Firmware
High Memory
High MMIO
All others
Address Range
Global Enable
G_SMRAME
0
1
1
1
1
defines when a SMM range is enabled. All the enable bits: G_SMRAME,
defines the access control of SMM memory regions from processors.
FEDA_0000h to FEDB_FFFF
interrupt transaction to
FEE0_0000h to FEEF_FFFFh (not
really memory space)
memory transaction to
FEE0_0000h to FEEF_FFFFh
FF00_0000h to FFFF_FFFFh
1_0000_0000 to MIR[x].LIMIT
(depending on the physical
memory external)
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
All Others (subtractive decoding)
High SMM Enable
H_SMRAM_EN
X
0
0
1
1
Conditions
Table 84, “SMM Memory Region Access Control from
TSEG Enable
TSEG_EN
X
0
1
0
1
See
from Processor”
Requests to SMM and VGA Spaces.”
Route to appropriate FSB(s).
Send to ESI to be master aborted.
Issue request to ESI.
Coherent request to main memory. Route to main
memory according to SC.MIR registers. Coherence
protocol is applied.
Route request to appropriate PCI Express* port
Issue request to ESI. There will be a subtractive
agent within ICH, where it will attempt to decode the
address. For undecoded address, transactions will be
aborted. Non-posted transactions will be
acknowledged with unsupported request (UR), and
posted request will be dropped.
Intel
Legacy SMM
Enabled?
Table 84, “SMM Memory Region Access Control
®
Yes
Yes
No
No
No
Intel
5100 MCH Chipset—System Address Map
®
5100 MCH Chipset Behavior
Table 83, “Enabled SMM
and
HIGH SMM
Enabled?
Table 85, “Decoding Processor
Order Number: 318378-005US
Yes
Yes
No
No
No
SMRAM Space
Extended
Enabled?
(TSEG)
Yes
Yes
No
No
No
July 2009
®