HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 309

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.13.1
Figure 25.
5.13.2
July 2009
Order Number: 318378-005US
Intel
Overview
The Intel
achieve superior I/O performance. The MCH PCI Express* ports are compliant with the
PCI Express* Base Specification, Rev. 1.0a.
A PCI Express* port is defined as a collection of bit lanes. Each bit lane consists of two
differential pairs in each direction (transmit and receive) as depicted in
PCI Express* Bit Lane.”
x4 PCI Express* Bit Lane
The raw bit-rate per PCI Express* bit lane is 2.5 Gb/s. This results in a real bandwidth
per bit lane pair of 250 MB/s given the 8b/10b encoding used to transmit data across
this interface. The result is a maximum theoretical realized bandwidth on a x4 PCI
Express* port of 1 GB/s in each direction.
Each of the Intel
directional bit lanes, and are referred to as a x4 port.
PCI Express* General Purpose Ports
PCI Express* Port 2 through Port 7 are configurable for general purpose I/O
applications and interfaces. The following port pairs can be combined to provide x8
ports, Ports 2 and 3, Ports 4 and 5, Ports 6 and 7. When combining ports the controlling
ports registers default to the lower port numbers address space. Thus when ports 4 and
5 are combined, the control registers are associated with port 4. These ports are
depicted in
General Purpose Ports.”
®
®
5100 Memory Controller Hub Chipset PCI Express* Port
®
5100 MCH Chipset utilizes general purpose PCI Express* high speed ports to
Figure 26, “Intel® 5100 Memory Controller Hub Chipset PCI Express*
5100 MCH Chipset
®
5100 MCH Chipset PCI Express* port are organized as four bi-
P
O
R
T
Rx
Tx
Rx
Tx
Rx
Tx
Rx
Tx
AC coupling capacitors
AC coupling capacitors
AC coupling capacitors
AC coupling capacitors
LINK (x4)
Lane 0
Lane 3
Lane 1
Lane 2
Intel
®
5100 Memory Controller Hub Chipset
Tx
Rx
Tx
Tx
Rx
Rx
Tx
Rx
P
O
R
T
Figure 25, “x4
Datasheet
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