HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet
HH80556KH0364M S LAGD
Specifications of HH80556KH0364M S LAGD
Related parts for HH80556KH0364M S LAGD
HH80556KH0364M S LAGD Summary of contents
Page 1
... Intel 5100 Memory Controller Hub Chipset Datasheet July 2009 Revision 005US Order Number: 318378-005US ...
Page 2
... Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725 visiting Intel’ ...
Page 3
... Primary PCI and Downstream Configuration Mechanism............................... 71 3.4 Device Mapping................................................................................................. 71 3.4.1 Special Device and Function Routing ......................................................... 72 3.5 I/O Mapped Registers ........................................................................................ 73 3.5.1 CFGADR: Configuration Address Register................................................... 73 3.5.2 CFGDAT: Configuration Data Register ....................................................... 74 July 2009 Order Number: 318378-005US ® Intel 5100 Memory Controller Hub Chipset Datasheet 3 ...
Page 4
... SEC_LT[7:2] - Secondary Latency Timer .................................... 118 3.8.8.13 IOBASE[7:2] - I/O Base Register............................................... 118 3.8.8.14 IOLIM[7:2] - I/O Limit Register ................................................. 118 3.8.8.15 SECSTS[7:2] - Secondary Status............................................... 119 ® Intel 5100 Memory Controller Hub Chipset Datasheet 4 ® Intel 5100 MCH Chipset—Contents July 2009 Order Number: 318378-005US ...
Page 5
... CORERRSTS[7:2,0] - Correctable Error Status ............................ 162 3.8.12.9 CORERRMSK[7:2,0] - Correctable Error Mask ............................. 162 3.8.12.10AERRCAPCTRL[7:2,0] - Advanced Error Capabilities and Control Register................................................................................. 162 3.8.12.11HDRLOG0[7:2,0] - Header Log 0............................................... 163 3.8.12.12HDRLOG1[7:2,0] - Header Log 1............................................... 163 July 2009 Order Number: 318378-005US ® Intel 5100 Memory Controller Hub Chipset Datasheet 5 ...
Page 6
... Internal First Non-Fatal Error Register ................. 180 3.8.13.18NERR_FAT_INT - Internal Next Fatal Error Register ...................... 180 3.8.13.19NERR_NF_INT - Internal Next Non-Fatal Error Register................. 181 3.8.13.20NRECINT - Non Recoverable Internal Intel Hub Chipset Error Log Register ................................................. 181 3.8.13.21EMASK_INT - Internal Error Mask Register.................................. 181 3.8.13.22ERR2_INT - Internal Error 2 Mask Register ................................. 182 3 ...
Page 7
... SPDDATA - Serial Presence Detect Status Register ...................... 214 3.9.11.2 SPDCMD: Serial Presence Detect Command Register ................... 214 3.10 DMA Engine Configuration Registers .................................................................. 216 3.11 CB_BAR MMIO Registers .................................................................................. 217 3.11.1 PEXCMD: PCI Command Register ........................................................... 220 July 2009 Order Number: 318378-005US Intel ® 5100 Memory Controller Hub Chipset Datasheet 7 ...
Page 8
... PCI Express* Per-Port Registers......................................................................... 251 3.12.0.1 NXTPPRSET2 - Next Per Port Register Set ................................... 251 3.12.0.2 NXTPPRSET3 - Next Per Port Register Set ................................... 251 ® Intel 5100 Memory Controller Hub Chipset Datasheet 8 ® Intel 5100 MCH Chipset—Contents July 2009 Order Number: 318378-005US ...
Page 9
... Registers Used for Address Routing......................................................... 270 4.4.2 Address Disposition for Processor ........................................................... 270 4.4.2.1 Access to SMM Space (Processor Only) ...................................... 272 4.4.3 Inbound Transactions ........................................................................... 274 4.5 I/O Address Map ............................................................................................. 275 4.5.1 Special I/O Addresses ........................................................................... 276 July 2009 Order Number: 318378-005US ® Intel 5100 Memory Controller Hub Chipset Datasheet 9 ...
Page 10
... Interrupt Redirection............................................................................. 294 5.4.3.1 XTPR Registers ....................................................................... 294 5.4.3.2 Redirection Algorithm .............................................................. 294 5.4.3.3 XTPR Update .......................................................................... 295 5.4.4 End Of Interrupt (EOI) .......................................................................... 295 5.5 I/O Interrupts ................................................................................................. 296 ® Intel 5100 Memory Controller Hub Chipset Datasheet 10 ® Intel 5100 MCH Chipset—Contents July 2009 Order Number: 318378-005US ...
Page 11
... IPI Ordering ........................................................................................ 298 5.7 Chipset Generated Interrupts ............................................................................ 299 ® 5.7.1 Intel 5100 Memory Controller Hub Chipset Generation of MSIs ................. 301 5.7.1.1 MSI Ordering in Intel 5.8 Software Guidance for MSI Handling .................................................................. 302 5.9 Legacy/8259 Interrupts.................................................................................... 303 5.10 Interrupt Swizzling .......................................................................................... 304 5.11 Interrupt Error Handling ................................................................................... 305 5 ...
Page 12
... Power Management.......................................................................................... 342 5.18.1 Supported ACPI States .......................................................................... 342 5.19 System Reset.................................................................................................. 342 ® 5.19.1 Intel 5100 Memory Controller Hub Chipset Reset Types ........................... 343 5.19.1.1 Power-Good Mechanism ........................................................... 343 5.19.1.2 Hard Reset Mechanism ............................................................. 344 5.19.1.3 Processor-Only Reset Mechanism............................................... 344 5.19.1.4 Targeted Reset Mechanism ....................................................... 344 5.19.1.5 BINIT# Mechanism .................................................................. 345 ® ...
Page 13
... Front Side Bus (FSB) Interface ............................................................... 381 6.2.3 DDR2 Interface .................................................................................... 381 6.2.4 PCI Express*/ESI Interface.................................................................... 382 6.2.5 SMBus Interfaces and Error Signals ........................................................ 383 6.2.6 JTAG Interface ..................................................................................... 384 6.2.7 Miscellaneous ...................................................................................... 384 July 2009 Order Number: 318378-005US ® Intel 5100 Memory Controller Hub Chipset Datasheet 13 ...
Page 14
... Power-Up ................................................................................................................60 6 PWRGOOD...............................................................................................................61 7 Hard Reset ..............................................................................................................61 8 RESETI# Retriggering Limitations ...............................................................................62 ® 9 Conceptual Intel 5100 Memory Controller Hub Chipset PCI Configuration Diagram ..........69 10 Type 1 Configuration Address to PCI Address Mapping...................................................71 ® 11 Intel 5100 Memory Controller Hub Chipset Implementation of SRID and CRID Registers ..95 12 PCI Express* Configuration Space ...
Page 15
... Memory Controller Hub Chipset Quadrant Map.......................................... 396 ® 63 Intel 5100 Memory Controller Hub Chipset Ballout Left Side (Top View)....................... 397 ® 64 Intel 5100 Memory Controller Hub Chipset Ballout Center (Top View).......................... 398 ® 65 Intel 5100 Memory Controller Hub Chipset Ballout Right Side (Top View)..................... 399 66 Bottom View ...
Page 16
... Memory Controller Hub Chipset PEXSTS and SECSTS Master/Data Parity Error RAS Handling ............................................................................................................... 120 54 GIO Port Mode Selection.......................................................................................... 127 55 IV Handling and Processing by Intel 56 Maximum Link Width Default Value for Different PCI Express* Ports .............................. 146 57 Negotiated Link Width For Different PCI Express* Ports After Training ........................... 148 58 Timing Characteristics of ERRPER ...
Page 17
... Intel 5100 Memory Controller Hub Chipset XAPIC Interrupt Message Routing and Delivery .......................................................... 293 94 Chipset Generated Interrupts................................................................................... 301 95 PCI Express* Link Width Strapping Options for Port CPCI Configuration in Intel Controller Hub Chipset............................................................................................ 312 96 Options and Limitations .......................................................................................... 312 ® 97 Intel 5100 Memory Controller Hub Chipset Lane Reversal Matrix ................................ 316 98 PCI Express* Credit Mapping for Inbound Transactions ...
Page 18
... Actions of Public TAP Instructions During Various TAP States ........................................ 393 141 Bypass Register Definition ....................................................................................... 393 ® 142 Intel 5100 Memory Controller Hub Chipset Device ID Codes ....................................... 394 ® 143 Intel 5100 Memory Controller Hub Chipset Signals By Ball ......................................... 400 ® 144 Intel 5100 Memory Controller Hub Chipset Signals By Name ...................................... 416 ® ...
Page 19
... Revision History—Intel 5100 MCH Chipset Revision History Date Revision Description • Change Bit description in 3” July 2009 005 • Changed DQS and DQS Lanes data in • Removed description from bit 31:0 in June 2009 004 Data Error Log Register A” on page Global Changes: • ...
Page 20
... Section 5.20.10, “Virtual Pin Ports” • Section 5.24, “Error List,” Table 123, “Intel® 5100 Memory Controller Hub Chipset Error List” added DMA Errors to Error List table. Others: • Section 1.3.1, “BIOS SelfTest Utility” removed; SelfTest password is no longer required. ...
Page 21
... Revision History—Intel 5100 MCH Chipset Revision Number Descriptions Revision Associated Life Cycle Milestone 0.0 POP L3 Closure 0.1–0.4 When Needed 0.5 Design Win Phase 0.6–0.7 When Needed 0.7 Simulations Complete 0.8–0.9 When Needed 1.0 First Silicon Samples 1.1– ...
Page 22
... Micro-FCBGA (Flip Chip Ball Grid Array) and 478-pin Micro-FCPGA (Flip Chip Pin Grid Array) packages for the Intel The Dual-Core Intel processor 5300 series return a processor signature of 06Fxh, and the Dual-Core Intel ® Xeon processor 5200 series, Quad-Core Intel ® ...
Page 23
... The unit of memory that is copied to and individually tracked in a cache. Specifically, 64 Cache Line bytes of data or instructions aligned on a 64-byte physical address boundary. Central Data Manager. A custom array within the Intel CDM temporary repository for system data in flight between the various ports: FSBs, DIMMs, ESI, and PCI Express* ...
Page 24
... Host This term is used synonymously with processor. 1. I/O 2. Ninth generation I/O controller hub with RAID, the Intel ICH9R The I/O controller hub component that contains the legacy I/O functions. It communicates with the MCH over a proprietary interconnect called the ESI interface. Implicit ...
Page 25
... July 2009 Order Number: 318378-005US Description ® 5100 Memory Controller Hub Chipset (formerly code-named San Clemente) 6 bytes per second) ® Intel 5100 Memory Controller Hub Chipset Datasheet 25 ...
Page 26
... A storage structure for information. Anything that enters a queue will exit eventually. The Queue most common policy to select an entry to read from the queue is FIFO (First In First Out). ® Intel 5100 Memory Controller Hub Chipset Datasheet 26 ® Intel 5100 MCH Chipset—Introduction Description Order Number: 318378-005US July 2009 ...
Page 27
... More narrowly, the circuitry required to convert incoming signals from the physical medium to more perceptible forms. ® 5100 Memory Controller Hub Chipset (formerly code-named San Clemente) ® ® Pentium 4 processor implements a subset of the enhanced mode. ® Intel 5100 Memory Controller Hub Chipset Datasheet 27 ...
Page 28
... MCH Chipset interface. The system bus in this document refers The Agent that sends a Packet across an interface regardless of whether it was the original generator of the packet. More narrowly, the circuitry required to drive signals onto the physical medium. ® Intel 5100 MCH Chipset—Introduction 2 C* Interface, July 2009 ...
Page 29
... Intel Electronic Design Kits (EDKs) provide online, real-time collateral updates. The following links take you to the EDK server and require you to log into Intel Link (IBL). • Quad-Core and Dual-Core Intel® Xeon® Processor 5000 Sequence with Intel® ...
Page 30
... Core™ Microarchitecture, Intel ® Xeon Processor External HW Spec System Management Bus (SMBus) Specification, Version 2.0 Notes: 1. Contact your Intel sales representative. Some documents may not be available at this time. ® 1.3 Intel 5100 Memory Controller Hub Chipset Overview ® Intel 5100 MCH Chipset-based platform, the MCH provides two FSB processor ...
Page 31
... Xeon processor 5400 series (45 nm process) have 2x4 MB and 2x6 MB shared L2 cache and a 266 MHz (1066 MT/s) system bus. The Dual-Core Intel processor 5100 series (65 nm process) and Dual-Core Intel series (45 nm process) have 4 MB and 6 MB shared L2 cache, respectively, and a 333 MHz (1333 MT/s) system bus ...
Page 32
... Non-Volatile Memory Storage Firware Hub ® Intel 5100 Memory Controller Hub Chipset Datasheet 32 P1 1066/1333 MTS System Bus Intel® 5100 Memory Controller Hub Chipset ESI 2 GB/s Intel® 82801IR I/O Controller Hub (ICH9R) LPC GLCI Intel Network Connection Gigabit PHY ...
Page 33
... Open Drain AGTL+ interface signal. The MCH integrates AGTL+ termination resistors, and supports VTT from 1. 1.2 V. Low Voltage TTL 3.3 V compatible signals Intel Figure 2, “Intel® 5100 and Figure 3, “Intel® illustrate the signals ® 5100 Memory Controller Hub Chipset ...
Page 34
... I/O Bidirectional (input/output) signal ® Intel 5100 Memory Controller Hub Chipset Datasheet 34 ® Intel 5100 MCH Chipset—Signal Description Stub Series Terminated Logic 2.6 V compatible signals CMOS buffers Expands to lists the reference terminology used for signal types. Description July 2009 Order Number: 318378-005US ...
Page 35
... Signal Description—Intel 5100 MCH Chipset 2.1 Processor Front Side Bus Signals 2.1.1 Processor Front Side Bus 0 Table 5. Processor Front Side Bus 0 Signals (Sheet Signal Name FSB0A[35:3]# I/O FSB0ADS# I/O FSB0ADSTB[1:0]# I/O FSB0AP[1:0]# I/O July 2009 Order Number: 318378-005US Type ...
Page 36
... I/O ® Intel 5100 Memory Controller Hub Chipset Datasheet 36 Intel Type Processor 0 Bus Initialization: FSB0BINIT# may be observed and driven by all processor FSB agents. If the FSB0BINIT# driver is enabled during power on configuration, FSB0BINIT# is asserted to signal any bus condition that prevents reliable future operation. ...
Page 37
... Signal Description—Intel 5100 MCH Chipset Table 5. Processor Front Side Bus 0 Signals (Sheet Signal Name FSB0D[63:0]# I/O FSB0DBI[3:0]# I/O FSB0DBSY# I/O FSB0DEFER# O FSB0DP[3:0]# I/O FSB0DRDY# I/O July 2009 Order Number: 318378-005US Type Processor 0 Data Bus: FSB0D[63:0]# are the data signals. These signals provide a 64-bit data path between the processor FSB agents ...
Page 38
... FSB0MCERR# is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. FSB0MCERR# assertion conditions are configurable at a system level. For more details regarding machine check architecture, refer to the Intel Architectures Software Developer’s Manual, Volume 3: System Programming Guide. ...
Page 39
... Core Intel Xeon Processor 5000 Sequence with Intel Controller Hub Chipset for Communications, Embedded, and Storage Applications – Platform Design Guide or Intel ® and SL9400 and Intel 5100 Memory Controller Hub Chipset for Communications and Embedded Applications – Platform Design Guide for the voltage value ...
Page 40
... FSB1BINIT# I/O ® Intel 5100 Memory Controller Hub Chipset Datasheet 40 Intel Type Processor 1 Address Bus: 36 FSB1A[35:3]# define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. ...
Page 41
... Signal Description—Intel 5100 MCH Chipset Table 6. Processor Front Side Bus 1 Signals (Sheet Signal Name FSB1BNR# I/O FSB1BPM[5:4]# I/O FSB1BPRI# O FSB1BREQ[1:0]# I/O FSB1D[63:0]# I/O July 2009 Order Number: 318378-005US Type Processor 1 Block Next Request: FSB1BNR# is used to assert a bus stall by any bus agent who is unable to accept new bus transactions ...
Page 42
... Intel 5100 Memory Controller Hub Chipset Datasheet 42 Intel Type Processor 1 Dynamic Data Bus Inversion: FSB1DBI[3:0]# are source synchronous and indicate the polarity of the FSB1D[63:0]# signals. The FSB1DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within, within a 16- bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group ...
Page 43
... FSB1MCERR# is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. FSB1MCERR# assertion conditions are configurable at a system level. For more details regarding machine check architecture, refer to the Intel Architectures Software Developer’s Manual, Volume 3: System Programming Guide. ...
Page 44
... Refer to the Quad-Core and Dual-Core Intel ® with Intel 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications – Platform Design Guide or Intel Duo Processors T9400 and SL9400 and Intel Chipset for Communications and Embedded Applications – Platform Design Guide for more details. ...
Page 45
... Signal Description—Intel 5100 MCH Chipset Table 7. DDR2 Channel 0 Signals (Sheet Name CH0_DCLKP[3] /CH0_CS[4]# CH0_DCLKP[2:0] CH0_CRES1 CH0_CRES2 CH0_CRESRET CH0_CS[5:4]# CH0_CS[3:0]# CH0_DQ[63:0] CH0_DQSN[17:0] CH0_DQSP[17:0] CH0_DRVCRES CH0_ODT[5:4] CH0_ODT[3:0] July 2009 Order Number: 318378-005US Type Memory Channel 0 DDR Clock Negative (Clock 3)/Chip Select (bit 4): When 48GB_Mode is strapped High, the signal functions as CH0_CS[4]# ...
Page 46
... Refer to the Quad-Core and Dual-Core Intel ® with Intel 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications – Platform Design Guide or Intel Duo Processors T9400 and SL9400 and Intel Chipset for Communications and Embedded Applications – Platform Design Guide for more details. ...
Page 47
... Signal Description—Intel 5100 MCH Chipset Table 8. DDR2 Channel 1 Signals (Sheet Name CH1_DCLKN[3] /CH1_CS[5]# CH1_DCLKN[2:0] CH1_DCLKP[3] /CH1_CS[4]# CH1_DCLKP[2:0] CH1_CRES1 CH1_CRES2 CH1_CRESRET CH1_CS[5:4]# CH1_CS[3:0]# CH1_DQ[63:0] CH1_DQSN[17:0] CH1_DQSP[17:0] CH1_DRVCRES July 2009 Order Number: 318378-005US Type Memory Channel 1 DDR Clock Negative (Clock 3)/Chip Select (Bit 5): When 48GB_Mode is strapped High, the signal functions as CH1_CS[5]# ...
Page 48
... Analog PEVSSBG Analog Power/ PEWIDTH[3:0] 2.3.2 PCI Express* Port 0, Enterprise South Bridge Interface (ESI) PCI Express* port port dedicated to providing the ESI link between the Intel 5100 MCH Chipset and the ICH9R. ® Intel 5100 Memory Controller Hub Chipset Datasheet 48 Intel ...
Page 49
... Signal Description—Intel 5100 MCH Chipset Table 10. PCI Express* Port 0, Enterprise South Bridge Interface (ESI) Signals Signal Name PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] 2.3.3 PCI Express* Port 2 PCI Express* port port. PCI Express* port 2 can be combined with PCI Express* port 3 to form a single PCI Express* x8 port. The combined x8 PCI Express* port is controlled by the configuration registers of the lowest x4 port number, the other port registers are inactive ...
Page 50
... Table 15. PCI Express* Port 6 Signals (Sheet Signal Name PE6RP[3:0] ® Intel 5100 Memory Controller Hub Chipset Datasheet 50 Intel Type PCI Express* Port 4 Positive Phase Inbound: I (Receive) Signals PCI Express* Port 4, Negative Phase Inbound: I (Receive) Signals PCI Express* Port 4, Positive Phase Outbound: ...
Page 51
... PCI Express* Graphics Port ® In the Intel 5100 MCH Chipset PCI Express* ports and 7 are combined to form a single high performance x16 graphics port. The combined x16 PCI Express* port is controlled by the configuration registers of the lowest x4 port number, port 4 in this case, the other port registers, ports 5, 6 and 7 are inactive ...
Page 52
... SPD0SMBCLK SPD0SMBDATA Notes: 1. These signals are Open Drain (OD) and require pull-ups, see Quad-Core and Dual-Core Intel Processor 5000 Sequence with Intel Embedded, and Storage Applications – Platform Design Guide or Intel T9400 and SL9400 and Intel Embedded Applications – Platform Design Guide for pull-up requirements. ...
Page 53
... JTAG specification support. Test Mode Select: TMS is a JTAG specification support signal used by debug tools. I See the Debug Port Design Guide for Intel Platforms (External Version) for further information. Test Reset: I TRST# resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset ...
Page 54
... Error Output: Error output signal recommended configuration: ERR[0] = Correctable and recoverable error from the memory subsystem ERR[1] = Uncorrectable error from the Intel ERR[2] = Fatal error from the Intel Note: The error assignments to the ERR[2:0] pins are configurable with the O use of the , “ ...
Page 55
... Signal Description—Intel 5100 MCH Chipset Table 21. Clocks, Reset and Miscellaneous Signals (Sheet Signal Name PWRGOOD PSEL[2:0] RESETI# RSVD Connect TDIOANODE TDIOCATHODE 2.8 Power and Ground Signals Table 22. Power and Ground Signals (Sheet Signal Name Core VCC (1.5 V): COREVCCA Analog Voltage for the PLL ...
Page 56
... The DDR2 memory interface power. VCC for PCI Express* ports (1.5 V): VCCPE The supply voltage for the PCI Express* ports. ® Intel 5100 Memory Controller Hub Chipset Datasheet 56 ® Intel 5100 MCH Chipset—Signal Description Description Order Number: 318378-005US July 2009 ...
Page 57
... GPIOSMBDATA SPD0SMBCLK SPD0SMBDATA CORECLK{P/N} FSBODTCRES FSBSLWCRES FSBSLWCTRL ASYNCRFSH TDIOANODE TDIOCATHODE XDPCOMCRES XDPD[15:0]# XDPSTB{P/N}# XDPODTCRES XDPSLWCRES July 2009 Order Number: 318378-005US Intel® 5100 MCH Chipset PEVCCA PEVCCBG PEVSSA PEVSSBG Front PCI Side Express* Bus 0 SMBus Interfaces Front Side Bus 1 ERR[2:0]# FSBCRES ...
Page 58
... XDPSLW CRES TRST# COREVCCA COREVSSA FSBVCCA V3REF VCCDDR VCCPE ® Intel 5100 Memory Controller Hub Chipset Datasheet 58 Intel Intel® 5100 MCH Chipset FSB0A[35:3] FSB0ADSTB[1:0]#, FSB0ADS# FSB0AP[1:0]# FSB0BINIT#, FSB0BNR# FSB0BPM [5:4]# FSB0BPRI# FSB0BREQ[1:0]# FSB0D[63:0]# Front FSB0DBI[3:0]# PCI FSB0DBSY#, FSB0DRDY# Side FSB0DEFER# ...
Page 59
... Signal Description—Intel 5100 MCH Chipset ® 2.9 Intel 5100 Memory Controller Hub Chipset Sequencing Requirements Power Plane and Sequencing Requirements: • Clock Valid Timing: • BUSCLK must be valid at least 2 ms prior to rising edge of PWRGOOD. See 5.22.1, “Reference Clocks” ...
Page 60
... Synchronized RESETI# is the RESETI# signal synchronized with the necessary internal clock domain, the PLLs are the internal PLLs locking to the BUSCLK signal and POC is Power-On Configuration, see ® Intel 5100 Memory Controller Hub Chipset Datasheet 60 ® Intel 5100 MCH Chipset—Signal Description Figure 5, “Power-Up.” T10 T11 T8 ...
Page 61
... Signal Description—Intel 5100 MCH Chipset 2.10.1.2 Power Good The PWRGOOD reset sequence is illustrated in Figure 6. PWRGOOD PWRGOOD RESETI# Synchronized RESETI# processor RESET# POC Straps T2 active Events PCI Express* ESI BUSCLK PLL's Sticky Bits Note: Synchronized RESETI# is the RESETI# signal synchronized with the necessary internal clock domain, the PLLs are the internal PLLs locking to the BUSCLK signal and POC is Power-On Configuration, see 2 ...
Page 62
... Figure 5 and Figure 6. Figure 4, Figure 5, and Figure 7. PWROK is an ICH9R Figure 5, Figure 6 and ® This is a special Dual-Core Intel ® Xeon processor 5100 series requirement to have a longer POC assertion setup time on the FSB. 5, Figure 6 and Figure 7. Figure 6 and Figure 7. Figure 5, Figure 6 ...
Page 63
... MCH Chipset, the T11 duration is implemented through a counter with max value of 162,000 core clocks. For 333 MHz, this gives a period of 486 µs for the POC setup time while @266 MHz, the period is 607.5 µs. Table 24, “Critical Intel® 5100 Memory Controller Hub Chipset Initialization Timings” summarizes the Intel ® ...
Page 64
... GB. See above DDR2 signal descriptions for more information. PCI Express* Port Width Strapping Pins: For strapping options refer to Table 95, “PCI Express* Link Width Strapping Other Options for Port CPCI Configuration in Intel® 5100 Memory Controller Hub Chipset” on page 312 ® 5100 MCH Chipset—Signal Description ® ...
Page 65
... PCI Express* Base Specification, Rev. 1.0a. The MCH supports registers in PCI Express* extended space. All registers in the Intel In addition, the MCH registers can be accessed by a memory mapped register access mechanism (as MMIO), a PCI configuration access mechanism (only PCI space registers), and register access mechanisms through the SMBus ...
Page 66
... Registers returned. (“Reserved” registers can bits in size). Writes to “Reserved” registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. ...
Page 67
... Register Description—Intel 5100 MCH Chipset expansion bus is physically attached to the ICH9R, and from a configuration perspective, appears hierarchical PCI bus behind a PCI-to-PCI bridge; therefore, it has a programmable PCI Bus number. The MCH contains 12 PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on PCI bus 0. • ...
Page 68
... Channel Control registers. These devices reside at DID 65F5h. • Device 22: Device 22, Function 0, Channel 1 Memory Map, Error Flag/Mask, and Channel 1 Control registers. These devices reside at DID 65F6h. ® Intel 5100 Memory Controller Hub Chipset Datasheet 68 ® Intel 5100 MCH Chipset—Register Description Order Number: 318378-005US July 2009 ...
Page 69
... PCI Express* Port 4 x4 PCI Express* Port 5 x4 PCI Express* Port 6 x4 PCI Express* Port 7 Intel® 5100 MCH Chipset 12 USB Ports, 2 EHCI Controllers 6 SATA July 2009 Order Number: 318378-005US ® 5100 Memory Controller Hub Chipset PCI Configuration Processor 0 PCI Config Window in I/O Space ...
Page 70
... PCI Bus 0. The ESI bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0. The ESI bridge passes PCI south bridge configuration requests to the south bridge. The ICH9R is the south bridge device for the Intel ® Intel ...
Page 71
... PCI bus address consisting of; Bus Number, Device Number and Function Number. Device configuration is based on the PCI Type 0 configuration conventions. All PCI devices within a Intel All MCH registers in the Intel ® All Intel 5100 MCH Chipset configuration registers reside in the configuration space defined by Bus, Device, Function, Register address ...
Page 72
... Mapped on FSB MCH Register Decoding Destination 3.4.1 Special Device and Function Routing All devices in the Intel Specially Handled by Intel® 5100 Memory Controller Hub Chipset” devices and functions that the MCH implements or routes specially. Table 28. Functions Specially Handled by Intel (Sheet Component ...
Page 73
... Reserved bits in registers 3.5 I/O Mapped Registers There are only two I/O addresses that affect the Intel first address is the DWORD location (CF8h) that references a read/write register named CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write register named CONFIG_DATA. These two addresses are used for the PCI CFCh/CF8h configuration access mechanism ...
Page 74
... Intel 5100 Memory Controller Hub Chipset Datasheet 74 Intel CFGE: Configuration Enable Unless this bit is set, accesses to the CFGDAT register will not produce a 0h configuration access, but will be treated as other I/O accesses. This bit is strictly an enable for the CFC/CF8 access mechanism and is not forwarded to ESI or PCI Express* ...
Page 75
... Register Description—Intel 5100 MCH Chipset Table 32. Mapping for Fixed Memory Mapped Registers (Sheet Register SPAD2 FE60_D800 SPAD3 FE60_DC00 SPADS0 FE60_E000 SPADS1 FE60_E400 SPADS2 FE60_E800 SPADS3 FE60_EC00 HECBASE FE61_6400 July 2009 Order Number: 318378-005US Memory Address Intel ® 5100 Memory Controller Hub Chipset ...
Page 76
... PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL ® Intel 5100 Memory Controller Hub Chipset Datasheet 76 Intel VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h 18h 1Ch 20h 24h 28h SVID 2Ch 30h ...
Page 77
... Register Description—Intel 5100 MCH Chipset Table 34. Device 0, Function 0: PCI Express* Extended Registers PEXENHCAP UNCERRSTS UNCERRMSK UNCERRSEV CORERRSTS CORERRMSK AERRCAPCTRL HDRLOG0 HDRLOG1 HDRLOG2 HDRLOG3 RPERRCMD RPERRSTS RPERRSID SCSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR July 2009 Order Number: 318378-005US ...
Page 78
... PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL ® Intel 5100 Memory Controller Hub Chipset Datasheet 78 Intel VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h PBUSN 18h IOBASE 1Ch 20h 24h 28h 2Ch ...
Page 79
... Register Description—Intel 5100 MCH Chipset Table 36. Device 2-3, Function 0: PCI Express* Extended Registers PEXENHCAP UNCERRSTS UNCERRMSK UNCERRSEV CORERRSTS CORERRMSK AERRCAPCTRL HDRLOG0 HDRLOG1 HDRLOG2 HDRLOG3 RPERRCMD RPERRSTS RPERRSID SCSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR PEX_UNIT_FERR PEX_UNIT_NERR July 2009 ...
Page 80
... PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL ® Intel 5100 Memory Controller Hub Chipset Datasheet 80 Intel VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h PBUSN 18h IOBASE 1Ch 20h 24h 28h 2Ch ...
Page 81
... Register Description—Intel 5100 MCH Chipset Table 38. Device 4, Function 0: PCI Express* Extended Registers PEXENHCAP UNCERRSTS UNCERRMSK UNCERRSEV CORERRSTS CORERRMSK AERRCAPCTRL HDRLOG0 HDRLOG1 HDRLOG2 HDRLOG3 RPERRCMD RPERRSTS RPERRSID SCSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR PEX_UNIT_FERR PEX_UNIT_NERR July 2009 ...
Page 82
... PMCAP PMCSR MSICTRL MSINXPTR MSIAR MSIDR PEXCAP PEXCAPL PEXDEVCAP PEXDEVSTS PEXDEVCTRL PEXLNKCAP PEXLNKSTS PEXLNKCTRL ® Intel 5100 Memory Controller Hub Chipset Datasheet 82 Intel VID 00h 04h PEXSLOTSTS RID 08h CLS 0Ch 10h 14h PBUSN 18h IOBASE 1Ch 20h 24h 28h 2Ch ...
Page 83
... Register Description—Intel 5100 MCH Chipset Table 40. Device 5-7, Function 0: PCI Express* Extended Registers PEXENHCAP UNCERRSTS UNCERRMSK UNCERRSEV CORERRSTS CORERRMSK AERRCAPCTRL HDRLOG0 HDRLOG1 HDRLOG2 HDRLOG3 RPERRCMD RPERRSTS RPERRSID SCSPCAPID PEX_ERR_DOCMD EMASK_UNCOR_PEX EMASK_COR_PEX EMASK_RP_PEX PEX_FAT_FERR PEX_NF_COR_FERR PEX_FAT_NERR PEX_NF_COR_NERR PEX_UNIT_FERR PEX_UNIT_NERR July 2009 ...
Page 84
... PAM1 PAM0 PAM6 PAM5 PAM4 EXSMRTOP EXSMRC SMRAMC HECBASE REDIRBUCKETS REDIRCTL FSBS0 FSBC1 FSBS1 ® Intel 5100 Memory Controller Hub Chipset Datasheet 84 Intel VID 00h 04h RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h SVID 2Ch 30h 34h 38h ...
Page 85
... Register Description—Intel 5100 MCH Chipset Table 42. Device 16, Function 0: Processor Bus 0 Error Registers July 2009 Order Number: 318378-005US NERR_NF_FS NERR_FAT_F FERR_NF_FS 100h B SB 104h NRECFSB 108h RECFSB 10Ch NRECADDRL 110h EMASK_FSB 114h ERR1_FSB 118h MCERR_FSB 11Ch 120h 124h 128h 12Ch ...
Page 86
... Table 43. Device 16, Function 0: Processor Bus 1 Error Registers ® Intel 5100 Memory Controller Hub Chipset Datasheet 86 ® Intel 5100 MCH Chipset—Register Description NERR_NF_FS NERR_FAT_F FERR_NF_FS 400h B SB 404h NRECFSB 408h RECFSB 40Ch NRECADDRL 410h EMASK_FSB 414h ERR1_FSB 418h MCERR_FSB 41Ch 420h ...
Page 87
... Register Description—Intel 5100 MCH Chipset Table 44. Device 16, Function 1: Memory Branch Map, Control, Errors DID CCR HDR SID MC MS SPDDATA SPDCMD ERRPER DDRFRQ MCA THRTHIGH THRTSTS1 THRTSTS0 July 2009 Order Number: 318378-005US VID 00h 04h RID 08h 0Ch 10h 14h ...
Page 88
... Table 45. Device 16, Function 1: Memory Gearing Registers MEMTOHOSTGRCFG0 MEMTOHOSTGRCFG1 MEMNDGRCFG0 MEMNDGRCFG1 HOSTTOMEMGRCFG0 HOSTTOMEMGRCFG1 ® Intel 5100 Memory Controller Hub Chipset Datasheet 88 ® Intel 5100 MCH Chipset—Register Description 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h ...
Page 89
... Register Description—Intel 5100 MCH Chipset Table 46. Device 16, Function 1: Memory DFx Registers MEM0EINJMSK0 MEM1EINJMSK1 MEM0EINJMSK1 MEM1EINJMSK0 MEMEINJADDRMAT MEMEINJADDRMSK July 2009 Order Number: 318378-005US 200h 204h 208h 20Ch 210h 214h 218h 21Ch 220h 224h 228h 22Ch 230h 234h 238h 23Ch 240h ...
Page 90
... Table 47. Device 16, Function 2: RAS DID CCR HDR SID FERR_Global NERR_Global ® Intel 5100 Memory Controller Hub Chipset Datasheet 90 Intel VID 00h 04h RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h SVID 2Ch 30h 34h 38h 3Ch NERR_NF_IN NERR_FAT_I 40h ...
Page 91
... Register Description—Intel 5100 MCH Chipset Table 48. Device 21, 22, Function 0: DIMM Map, Control, RAS DID CCR HDR SID SPCPS SPCPC July 2009 Order Number: 318378-005US VID 00h 04h RID 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h SVID 2Ch ...
Page 92
... Writes to reserved locations may cause system failure. 3.8.1 PCI Standard Registers These registers appear in every function for every device. ® Intel 5100 Memory Controller Hub Chipset Datasheet 92 Intel 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h ...
Page 93
... DID - Device Identification Register This 16-bit register combined with the Vendor Identification register uniquely identifies the Function within the MCH. Writes to this register have no effect. See “Functions Specially Handled by Intel® 5100 Memory Controller Hub Chipset” DID of each MCH function. Device: ...
Page 94
... The RID values for all devices and functions in the Intel controlled by the SRID/CRID register select flip flop, thus writing the key value (79h) to the RID register in Bus 0, Device 0, Function 0 sets all Intel registers to return the CRID. Writing to the RID register of other devices has no effect on the SRID/CRID register select flip-flop ...
Page 95
... Stepping Revision ID (SRID) The SRID is a 4-bit hardwired value assigned by Intel, based on product’s stepping. The SRID is not a directly addressable PCI register. The SRID value is reflected through the RID register when appropriately addressed. The 4 bits of the SRID are reflected as the two least significant bits of the major and minor revision field respectively. See Figure 11, “ ...
Page 96
... Intel 5100 Memory Controller Hub Chipset Datasheet 96 ® Intel 5100 MCH Chipset—Register Description Description Register-Level Programming Interface. This field identifies a specific programming interface (if any), that device independent software can use to interact with the device. There are no such interfaces defined for “Host Bridge” types, and this field is hardwired to 00h. ...
Page 97
... The default value specifies Intel. Each byte of this register will be writable once. Second and successive writes to a byte will have no effect. Description Subsystem Identification Number: The default value specifies Intel. Each byte of this register will be writable once. Second and successive writes to a byte will have no effect. Address Routing Registers 1 ...
Page 98
... Default 7:6 RV ® Intel 5100 Memory Controller Hub Chipset Datasheet 98 Intel 00 Reserved ESIENABLE0: 0F0000-0FFFFF Attribute Register This field controls the steering of read and write cycles that address the BIOS area from 0F0000 to 0FFFFF. Bit5 = Write enable, Bit4 = Read enable. 00 Encoding: Description 00: DRAM Disabled - All accesses are directed to ESI 01: Read Only - All reads are serviced by DRAM ...
Page 99
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 0 Offset: 5Ah Bit Attr Default 5:4 RW 3:2 RV 1:0 RW 3.8.3.3 PAM2 - Programmable Attribute Map Register 2 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0C 8000h -0C FFFFh. Device: ...
Page 100
... RV 1:0 RW ® Intel 5100 Memory Controller Hub Chipset Datasheet 100 Intel 00 Reserved ESIENABLE3: 0D 4000h - 0D 7FFFh Attribute Register This field controls the steering of read and write cycles that address the BIOS area from 0D 4000h -0D 7FFFh. Bit5 = Write enable, Bit4 = Read enable. 00 Encoding: Description 00: DRAM Disabled - All accesses are directed to ESI 01: Read Only - All reads are serviced by DRAM ...
Page 101
... Register Description—Intel 5100 MCH Chipset 3.8.3.6 PAM5 - Programmable Attribute Map Register 5 This register controls the read, write, and shadowing attributes of the BIOS areas which extend from 0E 0000h - 0E 7FFFh. Device: 16 Function: 0 Offset: 5Eh Bit Attr Default 7:6 RV 5:4 RW 3 ...
Page 102
... RO ® Intel 5100 Memory Controller Hub Chipset Datasheet 102 Intel 0 Reserved D_OPEN: SMM Space Open When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even 0 when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time ...
Page 103
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 0 Offset: 62h Bit Attr Default 5 RWL 2:1 RWL 0 RWL 3.8.3.10 EXSMRTOP - Extended System Management RAM Top Register This register defines the location of the Extended (TSEG) SMM range by defining the top of the TSEG SMM range (ESMMTOP). ...
Page 104
... Intel 5100 Memory Controller Hub Chipset Datasheet 104 Intel E_SMERR: Invalid SMRAM Access This bit is set when CPU has accessed the defined memory ranges in High SMM Memory and Extended SMRAM (T-segment) while not in SMM space and with the D-OPEN bit = 0. The MCH will set this bit if any In-Bound access from I/O device targeting SMM range that gets routed to the ESI port (master abort) ...
Page 105
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 0 Offset: 6Eh Bit Attr 11:8 RW 7:4 RW 3:0 RW 3.8.4.2 REDIRBUCKETS - Redirection Bucket Number Register This register allows software to read the current hardware bucket number assigned to each XTPR register. Device: 16 Function: 0 Offset: 68h Bit ...
Page 106
... The chipset associates BNR with BINIT and for CPUs that do NOT follow the “BNR independent of BINIT” feature set. 1: Enables the chipset to use the “BNR independent of BINIT” feature set, 0 i.e., no dependency is required between BNR and BINIT. Refer to the BNR#, BINIT# sampling rules in the RS - Intel ® Microarchitecture, Intel Pentium HW Spec ...
Page 107
... July 2009 Order Number: 318378-005US DCRT: ESI CPU Reset Done Ack Determinism Timer This field provides the determinism timer threshold for the Intel Chipset for handling the CPU_RESET_DONE/CPU_RESET_DONE_ACK message before deasserting the CPU_RESET#. It uses this 12-bit counter to schedule the CPU_RESET_DONE message on the ESI and then waits for the CPU_RESET_DONE_ACK message to come back and waits for the timer expiry before deasserting CPU_RESET# ...
Page 108
... Intel 5100 Memory Controller Hub Chipset Datasheet 108 Intel Scratch Pad value. These bits have no effect on the hardware. Default Scratch Pad value. These sticky bits have no effect on the hardware. Default SemaVal: Semaphore Value Can be written to any value. Value is cleared when there is a read. ® ...
Page 109
... MCH Chipset has seen Ab[22] asserted, indicating there are more than 1 processors present on this FSB. 2CORE: 2 Cores present ® 0 Set when the Intel 5100 MCH Chipset has seen Ab[30] asserted, indicating there is more than 1 core in a processor. Description Description Description ® ...
Page 110
... Hot Plug* etc. ® Intel 5100 Memory Controller Hub Chipset Datasheet 110 ® Intel Table 51. Index 1 is set if Ab[30] or Ab[22] Section 5.4.3, “Interrupt Redirection” Value Default CLUSTER: Global Cluster Mode (XTPR[0] only) Used in interrupt redirection for lowest priority delivery. Updated by every 0 xTPR_Update transaction on either bus (Aa[3]) ...
Page 111
... Standard PCI Header - This region closely resembles a standard PCI-to-PCI bridge header. • PCI Device Dependent Region - The region is also part of standard PCI configuration space and contains the PCI capability structures. For the Intel MCH Chipset, the supported capabilities are: — Message Signaled Interrupts — ...
Page 112
... PCI Express* ports uniquely while the ESI port is referred by index 0. ® Intel 5100 Memory Controller Hub Chipset Datasheet 112 ® Intel 5100 MCH Chipset—Register Description 0xFFF MCH Chipset Advanced Error Reporting 0x140 PCI Express* Advanced ...
Page 113
... ESI port to external interrupt controller where an interrupt can be generated to the CPU. This bit does not affect the ability of the Intel interrupt messages received at the PCI Express* port. However, this bit controls the generation of legacy interrupts to the ESI port for PCI 0 Express* errors detected internally in this port (e ...
Page 114
... MCH Chipset’s PCI Express* port using the above rules since BME is reset. However, in general illegal for an I/O device to issue inbound requests until the CPURESET# has been deasserted to prevent any possible malfunction in the Intel Chipset logic. MSE: Memory Space Enable Controls the bridge’ ...
Page 115
... Enable bit (PERRE). This applies only to parity errors that target the PCI Express* port interface (inbound/outbound direction). The detected parity error maps to B1, F6, M2 and M4 (uncorrectable data error from FSB, Memory ® or internal sources) of the Intel SSE: Signaled System Error 1: The PCI Express* port generated internal FATAL/NON FATAL errors (IO0- 0 IO17) through the ERR[2:0] pins with SERRE bit enabled. Software clears this bit by writing a ‘ ...
Page 116
... Function: 0 Offset: 0Dh Bit Attr Default 7:0 RO 3.8.8.5 BIST[7:2,0] - Built-In Self-test This register is used for reporting control and status information of BIST checks within a PCI Express* port not supported in the Intel Device: 7-2, 0 Function: 0 Offset: 0Fh Bit Attr Default 7:0 RO 3.8.8.6 ...
Page 117
... Register Description—Intel 5100 MCH Chipset 3.8.8.8 EXP_ROM[0]: Expansion ROM Registers The ESI port (device 0, function 0) does not implement any Base address registers in ® the Intel 5100 MCH Chipset from offset 10h to 24h. Similarly no Expansion ROM base address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in offset 28h ...
Page 118
... Default 7:4 RW ® Intel 5100 Memory Controller Hub Chipset Datasheet 118 Intel Slat_tmr: Secondary Latency Timer 00h Not applicable to PCI Express*. Hardwired to 00h. Section 3.8.8.14, “IOLIM[7:2] - I/O Limit Section 4.5.1, “Special I/O Addresses” IOBASE: I/O Base Address 0h Corresponds to A[15:12] of the I/O addresses at the PCI Express* port. ...
Page 119
... The PCI Express* port receives a Completion marked poisoned • The PCI Express* port poisons a write Request If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to Table 53, “Intel® 5100 Memory Controller Hub Chipset PEXSTS and SECSTS Master/Data Parity Error RAS Handling” ® ...
Page 120
... SECSTS[15].SDPE SECSTS[8].SMDPERR 1. In general, the DPE field is the superset of the MDPERR from a virtual PCI-to-PCI bridge perspective but there may be cases where a PEXSTS[8].MDPERR may not be logged in the PEXSTS[15].DPE field in the Intel MCH Chipset on the primary side. 3.8.8.16 MBASE[7:2] - Memory Base ...
Page 121
... Register Description—Intel 5100 MCH Chipset 3.8.8.17 MLIM[7:2]: Memory Limit This register controls the processor to PCI Express* non-prefetchable memory access routing based on the following formula as described above: MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address ...
Page 122
... Upper 32 Bits registers are implemented as read/write registers. ® Intel 5100 Memory Controller Hub Chipset Datasheet 122 Intel PMBASE: Prefetchable Memory Base Address 0h Corresponds to A[31:20] of the prefetchable memory address on the PCI Express* port. PMBASE_CAP: Prefetchable Memory Base Address Capability 0h – 32-bit Prefetchable Memory addressing 1h 1h – ...
Page 123
... Register Description—Intel 5100 MCH Chipset If a 64-bit prefetchable memory address range is supported, the Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers specify the upper 32-bits, corresponding to A[63:32], of the 64-bit base and limit addresses which specify the prefetchable memory address range. ...
Page 124
... Intel 5100 Memory Controller Hub Chipset Datasheet 124 Intel INTL: Interrupt Line BIOS writes the interrupt routing information to this register to indicate which 00h input of the interrupt controller this PCI Express* Port is connected to. Not used in MCH since the PCI Express* port does not have interrupt lines. ...
Page 125
... SBUSRESET field to train the link. When this SBUSRESET bit is cleared after the MCH enters the “Hot-Reset” ® state, the Intel 5100 MCH Chipset will initiate operations to move to “detect” 0 state and then train the link (polling, configuration, L0 (link-up)) after sending at least 2 TS1 and receiving 1 TS1 with the HotReset bit set in the training control field of TS1 and waiting for the Hot-Reset state ...
Page 126
... Perform a hard reset to the Intel The chipset will then use the values initialized in the PEXLWSTPCTRL.GPMNXT0(1) fields and train the links appropriately following the hard reset. The Intel Chipset will also provide status information to the software as to what link width it is currently using to train the link via PEXLWSTPCTRL.GPMCUR0(1) fields and the appropriate training mode, PEXLWSTPCTRL ...
Page 127
... Register Description—Intel 5100 MCH Chipset Device: 0 Function: 0 Offset: 40h Bit Attr Default 13:11 RO 000 10:8 RO 000 6:4 RWST 000 3:1 RWST 000 0 RWST 0 Table 54. GIO Port Mode Selection (Sheet GIO Port (IOU0) GPMNXT0[2:0] Port0 (IOU0) (ESI) 3'b000 x4 3'b001 invalid ...
Page 128
... DMA Engine configuration and memory mapped operations to device 8, function 0 and device 8, function 1 respectively. This is a special register intended to suppress the “yellow-bang” warning for the DMA Engine device for Intel customers who install non-standard operating systems without associated drivers. It can also be used as a defeature mode to block DMA Engine technology from being used ...
Page 129
... By the time the hint is used, 00 resources could be freed up and reused for the following requests Note: This mode of “00” is the preferred setting for the Intel MCH Chipset if COALESCE_EN=1 for software/BIOS 01: #CPL_ENTRIES_FREE will restrict coalesce_hint 10: if set then #PF_PEND will restrict coalesce hint 11: Minimum of coalesce_hint obtained from settings “ ...
Page 130
... Up to 128 bytes return if COALESCE_EN = 1 Note recommended that this field should not be set to 1 (256 bytes completion combining). COALESCE_FORCE: Force coalescing of accesses. ® When 1, forces the Intel 5100 MCH Chipset to wait for all coalescable data before sending the transaction as opposed to forwarding as much as possible Normal operation ...
Page 131
... DIS_APIC_EOI: Disable APIC EOI ® The Intel 5100 MCH Chipset will use this bit to decide whether end of interrupts (EOI) need to be sent to an APIC controller/bridge (e.g., Intel 6700PXH 64-bit PCI Hub) through this PCI Express* device EOIs are sent (disabled EOIs are dispatched to the APIC Controller. ...
Page 132
... PCI Hot Plug*. There is only one register for all PCI Express* ports and DMA Engine device that controls related I/O operations. ® Intel 5100 Memory Controller Hub Chipset Datasheet 132 ® Intel Default 0 Reserved PORTENABLE: PCI Express* port enable control 1: The PCI Express* port can be enabled by software and is available for use 1 0: The PCI Express* port is disabled and not available ...
Page 133
... PME_TURN_OFF: Send PME Turn Off Message ® When set, the Intel 5100 MCH Chipset will issue a PME Turn Off Message to all enabled PCI Express* ports excluding the ESI port. The Intel Chipset will clear this bit once the Message is sent. ® Note: ...
Page 134
... PCI Express* Power Management Capability Structure ® The Intel 5100 MCH Chipset PCI Express* port provides basic power management capabilities to handle PM events for compatibility. The PCI Express* ports can be placed in a pseudo D3 hot state but it does have real power savings and works were in the D0 mode ...
Page 135
... Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI 00h Bus Power Management Interface Specification, revision 1.1, for details. This is not implemented in the Power Management capability for the Intel 5100 MCH Chipset and is hardwired to 0h. BPCCEN: Bus Power/Clock Control Enable 0h This field is hardwired does not apply to PCI Express* ...
Page 136
... Scale” fields. PMEEN: PME Enable This field is a sticky bit and when set enables PMEs generated internally to 0h appear at the ICH9R through the “Assert(Deassert)_PMEGPE”message. This has no effect on the Intel generate PME events internally 0h Reserved PS: Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well ...
Page 137
... Disables MSI from being generated. ® 1: Enables the Intel 5100 MCH Chipset to use MSI messages to request context specific service for events such as PCI Hot Plug*, PM and RAS. AMSB: Address MSB This field specifies the 12 most significant bits of the 32-bit MSI address. ...
Page 138
... 13:11 RW 10:8 RW ® Intel 5100 Memory Controller Hub Chipset Datasheet 138 Intel AEXDSTID: Address Extended Destination ID 00h This field is not used by IA-32 processor. ARDHINT: Address Redirection Hint 0h 0: directed 1: redirectable ADM: Address Destination Mode 0h 0: physical 1: logical Reserved. 0h Not used since the memory write is D-word aligned Reserved ...
Page 139
... RV July 2009 Order Number: 318378-005US IV: Interrupt Vector The interrupt vector (LSB) will be modified by the Intel provide context sensitive interrupt information for different events that require attention from the processor, e.g., PCI Hot Plug*, Power Management and RAS 0h error events. Depending on the number of Messages enabled by the processor in 3.8.10.3, “ ...
Page 140
... Hardwired to 00h. 0h Reserved PIPD: Power Indicator Present on Device This bit when set indicates that a Power Indicator is implemented. 0 ® 0: PIPD is disabled in the Intel 1: Reserved AIPD: Attention Indicator Present This bit when set indicates that an Attention Indicator is implemented. 0 ® 0: AIPD is disabled in the Intel 1: Reserved ® ...
Page 141
... Order Number: 318378-005US ABPD: Attention Button Present This bit when set indicates that an Attention Button is implemented ABPD is disabled in the Intel 1: Reserved EPL1AL: Endpoint L1 Acceptable Latency This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. ...
Page 142
... The Intel 5100 MCH Chipset never sets or modifies the “No snoop bit” in the received TLP even if ENNOSNP is enabled. For outbound traffic, the Intel 5100 MCH Chipset does not need to snoop. APPME: Auxiliary Power Management Enable 1: Enables the PCI Express* port to draw AUX power independent of PME AUX power ...
Page 143
... MPS: Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express* port receiver, the Intel handle TLPs as large as the set value transmitter, it must not generate TLPs exceeding the set value. Permissible values that can be programmed ...
Page 144
... The Link Capabilities register identifies the PCI Express* specific link capabilities. ® Intel 5100 Memory Controller Hub Chipset Datasheet 144 ® Intel Reserved. TP: Transactions Pending 1: Indicates that the PCI Express* port has issued Non-Posted Requests which have not been completed device reports this bit cleared only when all Completions for any outstanding Non-Posted Requests have been received ...
Page 145
... More than 4 µs ® Note that the Intel 5100 MCH Chipset does not support L0s exit latency implementation and for safety, this field is set to the maximum value. ACTPMS: Active State Link PM Support This field indicates the level of active state power management supported on the given PCI Express* port ...
Page 146
... Default 15 ® Intel 5100 Memory Controller Hub Chipset Datasheet 146 Intel MLW: Maximum Link Width This field indicates the maximum width of the given PCI Express* Link attached to the port. 000001: x1 000100: x4 001000: x8 010000: x16 Others - Reserved See Table 56, “Maximum Link Width Default Value for Different PCI Express* Ports.” ...
Page 147
... ASTPMCTRL: Active State Link PM Control This field controls the level of active state power management supported on the given PCI Express* port. 00: Disabled 01 01: L0s Entry Supported 10: Reserved 11: L0s and L1 Supported Note: This has no effect on the Intel 0h Reserved Description ® 5100 MCH Chipset. . Description ® ...
Page 148
... RO 1. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel Note that this field is a don’t care until training is completed for the link. Software should not use this field to determine whether a link is up (enabled) or not. Table 57. ...
Page 149
... This field indicates the physical slot number connected to the PCI Express* 0h port. It should be initialized to 0 for ports connected to devices that are either integrated on the system board or integrated within the same silicon such as ® the Root port in the Intel 5100 MCH Chipset. 0h Reserved SPLS: Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Value ...
Page 150
... The PCI Hot Plug* capabilities of this register are not supported for the Intel default values to be maintained. The PEXSLOTSTS.CMDCMP bit will be set only when there is a unique change to the state of the PWRCTRL, PWRLED, ATNLED in this register ...
Page 151
... LEDs in the case of legacy card form factor for PCI Express* devices) 0h 11: Off Default is set to 11b (OFF) When this field is written, the Intel POWER_INDICATOR messages through the PCI Express* port. For legacy card-based PCI Express* devices, the event is signaled via the virtual pins of ® ...
Page 152
... MRL Closed 1: MRL Open CMDCMP: Command Completed ® This bit is set by the Intel 5100 MCH Chipset when the PCI Hot Plug* 0h controller completes an issued command and is ready to accept a new command subsequently cleared by software after the field has been read and processed. ...
Page 153
... It is subsequently cleared by software after the field has been read and processed. ABP: Attention Button Pressed ® This bit is set by the Intel 5100 MCH Chipset when the attention button is 0h pressed subsequently cleared by software after the field has been read and processed ...
Page 154
... Reserved. ® 5100 MCH Chipset—Register Description Intel® 5100 MCH Chipset Sends Desassert_HPGP E message via ESI when the respective bits PEXSLOTSTS str cleared (wired-OR) Intel® 5100 MCH Chipset Sends Desassert_INTx message via ESI when the respective bits of PEXSLOTSTS str ...
Page 155
... Register Description—Intel 5100 MCH Chipset Device: 7-2, 0 Function: 0 Offset: 88h Bit Attr Default 3.8.11.13 PEXRTSTS[7:2,0] - PCI Express* Root Status Register The PCI Express* Root Status register specifies parameters specific to the root complex port. Device: 7-2, 0 Function: 0 Offset: 8Ch Bit ...
Page 156
... Intel PTOV: PME_TO_Ack Timeout Value 00 (default 11: Reserved This register field provides the timer limit for the Intel keep track of the elapsed time from sending “PME_Turn_off” to receiving a “PME_TO_Ack”. 10h Reserved ® 5100 MCH Chipset—Register Description Description Section 3 ...
Page 157
... Register Description—Intel 5100 MCH Chipset Device: 0 Function: 0 Offset: D4h Bit Attr Default 3:0 RW 3.8.12 PCI Express* Advanced Error Reporting Capability 3.8.12.1 PEXENHCAP[7:2,0] - PCI Express* Enhanced Capability Header This register identifies the capability structure and points to the next structure. Device: ...
Page 158
... RWCST 11 RWST 4 RWCST ® Intel 5100 Memory Controller Hub Chipset Datasheet 158 ® Intel Default 0 IO10Err: Receiver Buffer Overflow Status 0 IO8Err: Unexpected Completion Status 0 IO7Err: Completer Abort Status 0 IO6Err: Completion Timeout Status 0 IO5Err: Flow Control Protocol Error Status 0 IO4Err: Poisoned TLP Status ...
Page 159
... Register Description—Intel 5100 MCH Chipset Device: 0 Function: 0 Offset: 104h Bit Attr 3 RWCST 3.8.12.4 UNCERRMSK[7:2] - Uncorrectable Error Mask This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being signaled. Device: 7-2 Function: 0 Offset: 108h Bit Attr 31: RWST RWST 17 RWST ...
Page 160
... RWST 14 RWST 13 RWST 12 RWST 11:6 RV ® Intel 5100 Memory Controller Hub Chipset Datasheet 160 ® Intel Default 0 IO2Msk: Received an Unsupported Request 0 Reserved 0 IO9Msk: Malformed TLP Status 0 IO10Msk: Receiver Buffer Overflow Mask 0 IO8Msk: Unexpected Completion Mask 0 IO7Msk: Completer Abort Status 0 IO6Msk: Completion Timeout Mask ...
Page 161
... Register Description—Intel 5100 MCH Chipset Device: 0 Function: 0 Offset: 10Ch Bit Attr 5 RWST 4 RWST 3 RWST 3.8.12.7 UNCERRSEV[7:2] - Uncorrectable Error Severity This register indicates the severity of the uncorrectable errors. An error is reported as fatal when the corresponding error bit in the severity register is set. If the bit is cleared, the corresponding error is considered non-fatal ...
Page 162
... AERRCAPCTRL[7:2,0] - Advanced Error Capabilities and Control Register This register identifies the capability structure and points to the next structure. ® Intel 5100 Memory Controller Hub Chipset Datasheet 162 ® Intel Section 3.8.12.25, “PEX_NF_COR_FERR[7:2,0] - Default 0h Reserved 0 IO16Err: Replay Timer Timeout Status 0h Reserved 0 ...
Page 163
... The Intel 5100 MCH Chipset does not generate ECRC. ECRCGENCAP: ECRC Generation Capable 0 ® The Intel 5100 MCH Chipset does not generate ECRC. FERRPTR: First error pointer The First Error Pointer is a read-only register that identifies the bit position 0h of the first error reported in the Uncorrectable Error status register. Left most error bit if multiple bits occurred simultaneously ...
Page 164
... Bit Attr 31:27 RO ® Intel 5100 Memory Controller Hub Chipset Datasheet 164 ® Intel 0h HDRLOGDW3: Header of TLP (DWORD 3) associated with error Default 0h Reserved EN_FAT_ERR: FATAL Error Reporting Enable 0 Enable interrupt on fatal errors when set. EN_NONFAT_ERR: Non-FATAL Error Reporting Enable 0 Enable interrupt on a non-fatal (uncorrectable) error when set ...
Page 165
... Register Description—Intel 5100 MCH Chipset Device: 7-2, 0 Function: 0 Offset: 130h Bit Attr 26 RWCST 5 RWCST 4 RWCST 3 RWCST 2 RWCST 1 RWCST 0 RWCST 1. This applies to both internal generated Root port errors and those messages received from an external source. 3.8.12.17 RPERRSID[7:2,0] - Error Source Identification Register ...
Page 166
... SCSPCAPID[7:2,0] - Intel specific Capability ID This register identifies the capability structure and points to the next structure. Device: 7-2, 0 Function: 0 Offset: 140h Bit Attr Default 31:20 RO 19:16 RO 15:0 RO 3.8.12.19 PEX_ERR_DOCMD[7:2,0] - PCI Express* Error Do Command Register Link Error Commands for doing the various signaling: ERR[2:0] and MCERR. ...
Page 167
... Register Description—Intel 5100 MCH Chipset 3.8.12.20 EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI This register masks (blocks) the detection of the selected error bits for the ESI port. When a specific error is blocked, it does NOT get reported or logged. Device: 0 Function: 0 Offset: ...
Page 168
... ® Intel 5100 Memory Controller Hub Chipset Datasheet 168 Intel 0h Reserved 0 IO19DetMsk: Surprise Link-down Mask 0 IO0DetMsk: Data Link Protocol Error Status 0h Reserved IO3DetMsk:Training Error Status This field should not be used for setting Training error severity due to a recent 0 PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is undefined ...
Page 169
... Register Description—Intel 5100 MCH Chipset 3.8.12.24 PEX_FAT_FERR[7:2,0] - PCI Express* First Fatal Error Register This register records the occurrence of the first unmasked PCI Express* FATAL errors and written by the MCH if the respective bits are not set prior. The classification of uncorrectable errors into FATAL is based on the severity level of the UNCERRSEV register described in Severity.” ...
Page 170
... RWCST 5 RWCST 4 RWCST ® Intel 5100 Memory Controller Hub Chipset Datasheet 170 ® Intel Default 0 First_NFAT_COR_Err_IO13: PEX - Bad TLP Error (correctable) 0 First_NFAT_COR_Err_IO12: PEX - Receiver Error (correctable) First_NFAT_COR_Err_IO11: PEX - Received Non Fatal (uncorrectable) 0 Error Message First_NFAT_COR_Err_IO10: PEX - Receive Buffer Overflow Error 0 (uncorrectable) ...
Page 171
... Register Description—Intel 5100 MCH Chipset Device: 7-2, 0 Function: 0 Offset: 15Ch Bit Attr 3 RWCST 2 RWCST 1 RWCST 0 RWCST 3.8.12.27 PEX_NF_COR_NERR[7:2,0] - PCI Express* Non Fatal or Correctable Next Error Register These errors are written by the MCH if the respective bits are set in PEX_NF_COR_FERR register. This register records the subsequent occurrences of unmasked PCI Express* NON-FATAL (Uncorrectable) and CORRECTABLE errors ...
Page 172
... Note that only the contents of FERR_GLOBAL affects the update of the any error log registers. ® Intel 5100 Memory Controller Hub Chipset Datasheet 172 ® Intel Default Next_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error 0 (uncorrectable) Default 0h Reserved First_FAT_VPP_Err: VPP Error for PCI Express* port 0 Records the occurrence of the first VPP error if this bit is not set prior ...
Page 173
... PCI Express* Device 3 Fatal Error Global_FERR_18: 0 PCI Express* Device 2 Fatal Error 0 Reserved Global_FERR_16: 0 ESI Fatal Error Global_FERR_15: 0 ® Internal Intel 5100 MCH Chipset Non-Fatal Error Global_FERR_14: 0 DMA Engine Device Non Fatal Error Global_FERR_13: 0 FSB1 Non-Fatal Error Global_FERR_12: 0 FSB0 Non-Fatal Error 0h Reserved ...
Page 174
... RWCST 19 RWCST 18 RWCST RWCST ® Intel 5100 Memory Controller Hub Chipset Datasheet 174 ® Intel Default Global_FERR_05: 0 PCI Express* Device 5 Non-Fatal Error Global_FERR_04: 0 PCI Express* Device 4 Non-Fatal Error Global_FERR_03: 0 PCI Express* Device 3 Non-Fatal Error Global_FERR_02: 0 PCI Express* Device 2 Non-Fatal Error 0 Reserved ...
Page 175
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 2 Offset: 44h Bit Attr 15 RWCST 14 RWCST 13 RWCST 12 RWCST 11 RWCST 7 RWCST 6 RWCST 5 RWCST 4 RWCST 3 RWCST 2 RWCST RWCST 3.8.13.3 FERR_FAT_FSB[1:0]: FSB First Fatal Error Register Device: 16 Function: 0 Offset: 480h, 180h Bit Attr 7 RWCST 4 RV ...
Page 176
... NRECFSB[1:0]: Non Recoverable FSB Error Log Register FSB Log registers for non recoverable errors when a fatal error is logged in its corresponding FERR_FAT_FSB Register ® Intel 5100 Memory Controller Hub Chipset Datasheet 176 ® Intel Default 0h Reserved 0 F7Err: Detected MCERR from a processor 0 F8Err: Detected BINIT from a processor 0 ...
Page 177
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 0 Offset: 484h, 184h Bit Attr 31:29 RV 28:24 ROST 23:21 ROST 20:16 ROST 15:8 ROST 7:0 ROST 3.8.13.8 RECFSB[1:0]: Recoverable FSB Error Log Register The following error log registers captures the FSB fields on the logging of an error in ...
Page 178
... This register enables the signaling of Err[1] when an error flag is set. Note that one and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and MCERR_FSB for each of the corresponding bits. ® Intel 5100 Memory Controller Hub Chipset Datasheet 178 ® Intel 00h A39DT32: FSB Address [39:32] Default 0h Reserved 1 F9Msk: FSB Protocol Error 1 ...
Page 179
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 0 Offset: 496h, 196h Bit Attr 15 RWST 7 RWST 6 RWST 5 RWST 4 RWST 0 RWST 3.8.13.14 ERR0_FSB[1:0]: FSB Error 0 Mask Register This register enables the signaling of Err[0] when an error flag is set. Note that one and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and MCERR_FSB for each of the corresponding bits ...
Page 180
... Bit Attr 7 RWCST 2 RWCST 1 RV ® Intel 5100 Memory Controller Hub Chipset Datasheet 180 Intel Default 1 F6Msk: Data Parity Error 0h Reserved 1 F2Msk: Unsupported Processor Bus Transaction 1 F1Msk: Request/Address Parity Error Default 0h Reserved 0h Reserved 0 B4Err: Virtual Pin Port Error (VPP_PEX) ...
Page 181
... RV 0 RWCST 3.8.13.20 NRECINT - Non Recoverable Internal Intel Hub Chipset Error Log Register This register will log non-recoverable errors (Fatal and Non Fatal) based on the internal MCH errors that originate from the FERR_FAT_INT, FERR_NF_INT described starting from Section 3.8.13.16, “FERR_FAT_INT - Internal First Fatal Error Register.” ...
Page 182
... Bit Attr 7 RWST 3 RWST 2 RWST RWST ® Intel 5100 Memory Controller Hub Chipset Datasheet 182 ® Intel Default 7h Reserved 1 B5Msk: Address Map Error 1 Reserved 1 B4Msk: Virtual Pin Port Error 1 B3Msk: Coherency Violation Error for EWB 1 Reserved 1 B1Msk: DM Parity Error Default 7h Reserved 1 ...
Page 183
... Register Description—Intel 5100 MCH Chipset 3.8.13.24 ERR0_INT - Internal Error 0 Mask Register This register enables the signaling of Err[0] when an error flag is set. Note that one and only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of the corresponding bits ...
Page 184
... RAS operations may lead to indeterministic behavior. Reserved INITDONE: Initialization Complete. This scratch bit communicates software ® state from the Intel 5100 MCH Chipset to BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. This bit has no effect on the ® Intel 5100 MCH Chipset operation ...
Page 185
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 1 Offset: 40h Bit Attr Default RWC 0 3 3.9.1.2 MCA - Memory Control Settings A Additional miscellaneous control not reflected in other registers. Device: 16 Function: 1 Offset: 58h Bit Attr Default 31: 27:0 RV DB21915h 3.9.1.3 MS: Memory Status Register Miscellaneous status not reflected in other registers ...
Page 186
... B0: The value of the bit provides the strapped state of the 48GB_Mode input. The 48GB_Mode input is strapped High for 48 GB support over six ranks/channel. The 48GB_Mode input is strapped Low for 32 GB support over four ranks/channel. The BIOS can read this bit to determine the mode of operation of the Intel Memory Controller Hub Chipset. Reserved ...
Page 187
... Register Description—Intel 5100 MCH Chipset Device: 16 Function: 1 Offset: 50h Bit Attr Default 31:0 RW 3.9.1.6 MTR[1:0][5:0] - Memory Technology Registers These registers define the organization of the DIMM’s. There is one MTR for each rank. The parameters for these devices can be obtained by serial presence detect. ...
Page 188
... Memory Throttling Control Registers ® The Intel 5100 MCH Chipset employs activation based throttling where the number of activates to a given rank are monitored and possibly limited as required. There are two levels of throttling, low (normal operation) and high (activations throttling triggered), and the levels of activity permitted at both these levels are selected by the BIOS. ® ...
Page 189
... Register Description—Intel 5100 MCH Chipset Note that throttling decreases performance and increases memory access latency in heavy traffic. Extremely low values (below 10h) will lead to dramatically increased latency for reads which could result in requestor timeouts, etc. Note that throttling must always be disabled for RCVEN calibration. ...
Page 190
... This field will be set by the Intel 5100 MCH Chipset and the value of this field will vary between THRTLOW and THRTHIGH registers based on the throttling. Description THRTHIGHLM: Thermal Throttle High Limit A throttling level that is applied when the THRTSTS ...
Page 191
... A base throttling level that is applied when the THRTSTS.GBLTHRT* bit is not set by the Global Throttling Window logic. Note: The GBLTHRT internal signal from the Intel open loop combinatorial cluster before it is latched in the THRTSTS.GLTHRT register. This will prevent any stale/delayed information from being used for the open loop throttling logic ...
Page 192
... Intel 5100 Memory Controller Hub Chipset Datasheet 192 ® Intel 5100 MCH Chipset—Register Description Description DDRFRQ: CORE:DDR Frequency Ratio (write new ratio to these bits) ‘000’ = 1:1. BUSCLK=266 MHz, DDR=533 MHz. ‘001’ = 1:1. BUSCLK=333 MHz, DDR=667 MHz. ‘010’ = 4:5. BUSCLK=266 MHz, DDR=667 MHz. ...
Page 193
... Register Description—Intel 5100 MCH Chipset MEM to Host Gear Ratio Mux Table 61. FSB: Memory Frequency 333:333 267:267 333:267 267:333 3.9.3.4 MEMNDGRCFG0: MEM Next Data Gear Ratio Configuration 0 This register consists of 8 nibbles of mux select data for the proper selection of gearing behavior in the MC. This is the first of two registers to control the behavior for the DRAM to host (Northbound) data flow for the “ ...
Page 194
... Bit Attr Default 31:0 RWST 00000000h ® Intel 5100 Memory Controller Hub Chipset Datasheet 194 ® Intel 5100 MCH Chipset—Register Description for MEMNDGRCFG1 Gear Ratio Option 1:1 only 5:4 conservative 4:5 conservative Description HSTMEMGRMUX: Host to MEM Clock Gearing mux selector. ...
Page 195
... MHz) FAW The actual register filed names are always T clock cycles). BL, the burst length, is always set to eight (four clock cycles) for Intel 5100 MCH Chipset. Most of the bit fields represent timing rules that define a minimum separation of events that will be enforced by the device. Transactions that would break one of the timing rules (if issued to the DIMMs) are deemed to be “ ...
Page 196
... Intel 5100 Memory Controller Hub Chipset Datasheet 196 ® Intel 5100 MCH Chipset—Register Description Description T : Electrical Throttling Window FAW This parameter is the smallest window over which four activations can be issued to a given rank: no more than four activations can be issued within any given (sliding) T window ...
Page 197
... Register Description—Intel 5100 MCH Chipset 3.9.4.2 DRTB[1:0]: DDR Timing Register B This register defines timing parameters that work with all DDR ports in the appropriate channel. This register must be set to provide timings that satisfy the specifications of all detected DDR ports. For example, if DDR ports have different T be used to program this register ...
Page 198
... Intel 5100 Memory Controller Hub Chipset Datasheet 198 Intel TOLM: Top Of Low Memory This register defines the maximum DRAM memory address that lies below 4 GB. It does not denote the actual low MMIO gap but the upperbound of the system low memory. ...
Page 199
... Register Description—Intel 5100 MCH Chipset MIR updates can only occur in the “Reset”, “Ready”, “Fault”, and “Disabled” configuration register states. Table 66. Interleaving of Address Is Governed by MIR[i] if Limit with Respect to TOLM if MIR[i].LIMIT[11:0] <= TOLM if MIR[i].LIMIT[11:0] > TOLM > MIR[i- 1].LIMIT[11:0] if MIR[i].LIMIT[11:0] > ...
Page 200
... Bit Attr Default 31: RWCST ® Intel 5100 Memory Controller Hub Chipset Datasheet 200 Intel 0h Reserved Chan_Indx: Logs channel in which the highest-order error occurred 0 Valid only when one of the lower bits is non-zero. 00h Reserved 0 M21Err: Spare Copy Completed 0 M20Err: Spare Copy Initiated ...