HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 64

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.11
2.12
2.12.1
Table 25.
Intel
Datasheet
64
®
5100 Memory Controller Hub Chipset
Intel
Reference Platform (CRP) Reset Topology
Typical implementation and routing of PWRGOOD, system Reset and interrupt
connections for a Intel
Core and Dual-Core Intel
Controller Hub Chipset for Communications, Embedded, and Storage Applications –
Platform Design Guide and Intel
Intel
Applications – Platform Design Guide.
Signals Used as Straps
Functional Straps
The PEWIDTH signals are used to determine the widths of the six PCI Express* ports
and 48 GB mode signals determine which DDR2 memory mode to enable.
Signals Used as Straps
48GB_Mode
PEWIDTH[3:0]
Signal Name
transition on the clock signal within t
specification) after deassertion of PWRGOOD to prevent clock glitches. Within these
constraints, an in-progress write address will not be corrupted.
®
5100 Memory Controller Hub Chipset for Communications and Embedded
®
5100 Memory Controller Hub Chipset Customer
Power/
Power/
Other
Other
Type
®
5100 MCH Chipset-based platform are described in the Quad-
48 GB DDR2 Memory Mode Selection:
The strapping of this pin determines the maximum memory supported, 32 GB
or 48 GB. See above DDR2 signal descriptions for more information.
PCI Express* Port Width Strapping Pins:
For strapping options refer to
Options for Port CPCI Configuration in Intel® 5100 Memory Controller Hub
Chipset” on page 312
®
Xeon
®
®
Core™2 Duo Processors T9400 and SL9400 and
Processor 5000 Sequence with Intel
R
= 1 µs (Atmel* AT24C01 timing
Table 95, “PCI Express* Link Width Strapping
Intel
Description
®
5100 MCH Chipset—Signal Description
Order Number: 318378-005US
®
5100 Memory
July 2009