HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 217

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11
Table 71.
July 2009
Order Number: 318378-005US
INTRCTRL
PERPORT_OFFSET
CS_STATUS
GENCTRL
CB_BAR MMIO Registers
These MMIO registers are placed in the configuration ring for CPU MMIO accesses but
the device will be able to read/write to this space using the fast, bypass inbound access
method. Note that this MMIO space is not accessible by MMCFG or CFC/CF8 from the
FSB and the mapping to the configuration space is an internal MCH feature to suit the
microarchitecture.
Device 8, Function 1, DMA Engine DMABAR MMIO Registers (General, DMA
Channel 0) Mapped through Configuration
CHAN_SYSERR_MSK0
CHAN_SYSERR_MSK1
CHAN_SYSERR_MSK2
CHAN_SYSERR_MSK3
ATTNSTATUS
®
5100 MCH Chipset
XFERCAP
INTRDELAY
CHANCNT
CBVER
0Ch
1Ch
2Ch
3Ch
4Ch
5Ch
6Ch
7Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h
58h
60h
64h
68h
70h
74h
78h
CHDSCSTATE
CHANSTATE0
FETCHSTATE
ERRNOTIFYS
TATE0
0
0
DMA_COMP0
CHANDSCSRCADDRH0
CHANDSCDSTADDRH0
CHANNXTDSCADDRH0
CHANDSCSRCADDRL0
CHANDSCDSTADDRL0
CHANNXTDSCADDRL0
CHANSRCLENREMPF0
CHANDSTLENREMPF0
CHANSRCLENREMF0
CHANDSTLENREMF0
CHANSRCADDRPFL0
CHANDSTADDRPFL0
CHANSRCADDRFL0
CHANDSTADDRFL0
CHANXFERSIZE0
Intel
CHANERRMSK0
CHANDSCCTL0
CHAINADDR0
CHANCMP0
CHANSTS0
CHANERR0
CDAR0
®
5100 Memory Controller Hub Chipset
CHANCTRL0
CHANSRCAD
CHANSRCAD
CHANDSTAD
CHANDSTAD
CHANCMD0
DRPFH0
DRPFH0
DRFH0
DRFH0
Datasheet
ACh
BCh
CCh
D0h
D4h
D8h
DCh
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
B0h
B4h
B8h
C0h
C4h
C8h
E0h
E4h
E8h
ECh
FCh
F0h
F4h
F8h
217