HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 278

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.0
5.1
5.1.1
Intel
Datasheet
278
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5100 Memory Controller Hub Chipset
Functional Description
This section describes each of the Intel
units including the Dual Independent Bus (DIB) processor Frontside Bus (FSB)
interface, the PCI Express* ports, system memory controller, power management and
clocking.
Processor Front Side Buses
The Intel
the Dual-Core Intel
5300 series, Dual-Core Intel
Xeon
771-land, FC-LGA4 (Flip Chip Land Grid Array 4) package for the processors.
The Intel
the Intel
This Intel
Chip Ball Grid Array) and 478-pin Micro-FCPGA (Flip Chip Pin Grid Array) packages for
the processors.
The Intel
bus running off a 266/333 MHz system clock. Each of the two processor FSB DIBs
support peak address generation rates of 266/333 Million Addresses/second. Each FSB
data bus is a quad pumped 64-bit interface which allows peak bandwidths of 8.5/10.7
GB/s (1066/1333 MT/s). The MCH supports 36-bit host addressing. The MCH supports
up to 32 GB or 48 GB depending upon the mode of the processor memory address
space. Host-initiated I/O cycles are decoded to PCI Express*, ESI interface or MCH
configuration space. Host-initiated memory cycles are decoded to PCI Express*, ESI or
system memory.
FSB Overview
The Intel
independent, processor front side buses (FSB). These two buses are referred to as Dual
Independent Buses (DIB). The MCH may complete deferrable transactions with either
defer-replies or in-order responses. Data transactions on the FSBs are optimized to
support 64 byte cache lines.
Each processor FSB contains a 36 bit address bus, a 64-bit data bus, and associated
control signals. The FSB utilizes a split-transaction, deferred reply protocol. The FSB
uses source-synchronous transfer of address and data to improve performance. The
FSB address bus is double pumped (2x) with address strobe (ADS) being sourced every
other clock. The address bus generates a maximum bandwidth of 266/333 Million
Addresses/second (MA/s).
The FSB data bus is quad pumped (4x) and supports peak bandwidths of 8.5/10.7 GB/
s (1066/1333 MT/s). Parity protection is applied to the data bus. This yields a combined
bandwidth of 17/21 GB/s for both FSBs.
Interrupts are also delivered via the FSB.
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processor 5400 series. This Intel
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®
®
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Core™2 Duo Processor T9400 as part of Uni-Processor (UP) system designs.
5100 MCH Chipset provides the dual independent processor bus supporting
5100 MCH Chipset also provides a single Front Side Bus (FSB) supporting
5100 MCH Chipset supports 1066/1333 MT/s FSB which is a quad-pumped
5100 MCH Chipset is the only priority agent for two point to point,
5100 MCH Chipset-based platform supports 479-ball Micro-FCBGA (Flip
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Xeon
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processor 5100 series, Quad-Core Intel
Xeon
®
processor 5200 series, and Quad-Core Intel
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5100 MCH Chipset interfaces and functional
5100 MCH Chipset-based platform supports a
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
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Xeon
®
processor
July 2009
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