HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 112
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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Figure 12.
3.8.8
Intel
Datasheet
112
®
5100 Memory Controller Hub Chipset
PCI Express* Configuration Space
Figure 12, “PCI Express* Configuration Space”
addresses for each of the PCI Express* ports as defined in the PCI Express* Base
Specification, Rev. 1.0a. It is also compatible with the standard PCI 2.3 capability
structure and comprises of a linked list where each capability has a pointer to the next
capability in the list. For PCI Express* extended capabilities, the first structure is
required to start at 100h offset.
PCI Express* Header
The following registers define the standard PCI 2.3 compatible and extended PCI
Express* configuration space for each of the PCI Express* x4 links in the MCH. Unless
otherwise specified, the registers are enumerated as a vector [2:7] mapping to each of
the six PCI Express* ports uniquely while the ESI port is referred by index 0.
PCI Express* Advanced
PCI Express* Capability
MSI Capability
Advanced Error
PM Capability
Error Reporting
MCH Chipset
PCI-to-PCI
Reporting
Bridge
CAPPTR
Intel
shows the configuration register offset
0x140
0x100
0x40
0x00
0xFFF
®
5100 MCH Chipset—Register Description
1220071543
Order Number: 318378-005US
July 2009
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