HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 35

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
2.1
2.1.1
Table 5.
July 2009
Order Number: 318378-005US
Processor Front Side Bus Signals
Processor Front Side Bus 0
Processor Front Side Bus 0 Signals (Sheet 1 of 5)
FSB0A[35:3]#
FSB0ADS#
FSB0ADSTB[1:0]#
FSB0AP[1:0]#
Signal Name
®
5100 MCH Chipset
I/O
I/O
I/O
I/O
Type
Processor 0 Address Bus:
FSB0A[35:3]# define a 2
1 of the address phase, these signals transmit the address of a transaction. In
sub-phase 2, these signals transmit transaction type information.
FSB0A[35:3]# are protected by parity signals FSB0AP[1:0]#. FSB0A[35:3]#
are source synchronous signals and are latched into the receiving buffers by
FSB0ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset
of the FSB0A[35:3]# lands to determine their power-on configuration.
FSB0A[35:3]# connect to the processor address bus. During processor cycles,
FSB0A[35:3]# are inputs. The MCH drives FSB0A[35:3]# during snoop cycles
on behalf of ESI and Secondary PCI initiators. FSB0A[35:3]# are transferred at
2x rate. Note that the address is inverted on the processor bus.
Processor 0 Address Strobe:
FSB0ADS# is asserted to indicate the validity of the transaction address on
FSB0A[35:3]#. All bus agents observe the FSB0ADS# activation to begin parity
checking, protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction. The processor bus
owner asserts FSB0ADS# to indicate the first of two cycles of a request phase.
Processor 0 Address Strobe:
FSB0ADSTB[1:0]# are source synchronous strobes used to transfer
FSB0A[35:3]# and FSB0REQ[4:0]# at the 2x transfer rate on the strobes rising
and falling edges.
Processor 0 Address Parity:
FSB0AP[1:0]# provide parity protection on the address bus. FSB0AP[1:0]# are
driven by the request initiator along with FSB0ADS#, FSB0A[35:3]#, and the
transaction type on the FSB0REQ[4:0]# signals. A correct parity signal is high if
an even number of covered signals are low and low if an odd number of covered
signals are low. This allows parity to be high when all the covered signals are
high. The following defines the coverage model of these signals.
Request Signals
FSB0REQ[4:0]#
FSB0A[35:24]#
FSB0A[23:3]#
FSB0A[35:17]#
FSB0REQ[4:0],
FSB0A[16:3]#
Signals
36
Subphase 1
FSB0AP[0]#
FSB0AP[1]#
FSB0AP[1]#
-byte physical memory address space. In sub-phase
Associated Strobes
FSB0ADSTB[0]#
FSB0ADSTB[1]#
Description
Intel
®
5100 Memory Controller Hub Chipset
Subphase 2
FSB0AP[1]#
FSB0AP[0]#
FSB0AP[0]#
Datasheet
35