HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 101

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.3.6
3.8.3.7
July 2009
Order Number: 318378-005US
PAM5 - Programmable Attribute Map Register 5
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 0000h - 0E 7FFFh.
PAM6 - Programmable Attribute Map Register 6
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 8000h - 0E FFFFh.
Device:
Function:
Offset:
Device:
Function:
Offset:
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Bit
Bit
®
Attr
Attr
RW
RW
RW
RW
RV
RV
RV
RV
5100 MCH Chipset
16
0
5Eh
16
0
5Fh
Default
Default
00
00
00
00
00
00
00
00
Reserved
ESIENABLE5: 0E4000-0E7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E4000-0E7FFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE5: 0E0000-0E3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E0000-0E3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
ESIENABLE6: 0E C000h - 0E FFFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E C000h - 0E FFFFh.
Bit5 = Write enable, Bit4 = Read enable.
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE6: 0E 8000h - 0E BFFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E 8000h - 0E BFFFh.
Bit1 = Write enable, Bit0 = Read enable
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
101