HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 25

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Introduction—Intel
Table 1.
July 2009
Order Number: 318378-005US
Terminology (Sheet 3 of 6)
Intel
Chipset
Isochronous
Layer
Legacy
Line
Link
Lock
LSb
LSB
Master
Master Abort
MB/s
MC
MCH
Mem
Memory Issue
Mesochronous
Metastability
Mirroring
MMCFG
MMIO
MSb
MSB
MTBF
Non-Coherent
Outbound
Outgoing
Packet
Page Hit.
Page Miss (Empty
Page)
®
Terminology
5100 MCH Chipset
®
5100 MCH
Intel
A classification of transactions or a stream of transactions that require service within a
fixed time interval.
A level of abstraction commonly used in interface specifications as a tool to group
elements related to a basic function of the interface within a layer and to identify key
interactions between layers.
Functional requirements handed down from previous chipsets or PC compatibility
requirements from the past.
Cache line.
The layer of an interface that handles flow control and often error correction by retry.
A sequence of transactions that must be completed atomically.
Least Significant Bit
Least Significant Byte
A device or logical entity that is capable of initiating transactions. A Master is any potential
Initiator.
A response to an illegal request. Reads receive all ones. Writes have no effect.
Megabytes per second (10
Memory Controller
The Memory Controller Hub component that contains the processor interface, DRAM
controller, PCI Express* interface. It communicates with the I/O controller hub (ICH9R)
over a proprietary interconnect called the Enterprise South Bridge Interface (ESI).
Used as a qualifier for transactions that target memory space. (for example, a Mem read
to I/O).
Committing a request to DDR or, in the case of a read, returning the read header.
Distributed or common referenced clock
A characteristic of flip flops that describes the state where the output becomes non-
deterministic. Most commonly caused by a setup or hold time violation.
RAID-1. This terminology is utilized in this document.
Memory Mapped Configuration. A memory transaction that accesses configuration space.
Memory Mapped I/O. Any memory access to PCI Express*.
Most Significant Bit
Most Significant Byte
Mean Time Between Failure
Transactions that may cause the processor’s view of memory through the cache to be
different with that obtained through the I/O subsystem.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
A transaction or completion that exits the MCH. Peer-to-peer Transactions that occur
between two devices below the PCI Express* or ESI ports.
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
An access to an open page, or DRAM row. The data can be supplied from the sense amps
at low latency.
An access to a page that is not buffered in sense amps and must be fetched from DRAM
array. Address Bit Permuting Address bits are distributed among channel selects, DRAM
selects, bank selects to so that a linear address stream accesses these resources in a
certain sequence.
®
5100 Memory Controller Hub Chipset (formerly code-named San Clemente)
6
bytes per second)
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
25