HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 317

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.13.6
Figure 31.
5.13.6.1
5.13.6.2
July 2009
Order Number: 318378-005US
Link Layer
The Data Link Layer of the PCI Express* protocol is primarily responsible for data
integrity. This is accomplished with the following elements:
Figure 31, “PCI Express* Packet Visibility By Link Layer”
layer on a PCI Express* packet. There are two types of packets: data link layer packets
(DLLP) and Transaction Layer Packets (TLP). Data Link layer packets are sent between
the Link layers of each PCI Express* device and do not proceed to the Transaction
Layer.
For Transaction layer packets (TLP), the link layer is responsible for prepending
sequence numbers and appending 32-bit CRC. The grayed out segment is not decoded
by the Data Link layer.
PCI Express* Packet Visibility By Link Layer
Data Link Layer Packets (DLLP)
Refer to PCI Express* Base Specification, Rev. 1.0a for an explicit definition of all the
fields in a Data Link Layer packet.
DLLPs are used to ACK or NAK packets as they are sent from the transmitter to the
receiver. They are sent by the receivers of the packet to indicate to the transmitter that
a packet was successfully received (ACK) or not (NAK). DLLPs are also used to
exchange credit information between the transmitter and receiver.
DLLPs are protected with 16-bit CRC. If the CRC of a received DLLP indicates an error,
the DLLP is dropped. This is safe because the PCI Express* protocol supports dropping
these packets and the next DLLP allows the transmitter to process successfully.
ACK/NAK
The Data Link layer is responsible for ensuring that packets are successfully
transmitted between PCI Express* agents. PCI Express* implements an ACK/NAK
protocol to accomplish this. Every packet is decoded by the physical layer and
forwarded to the link layer. The CRC code appended to the packet is then checked. If
this comparison fails, the packet is “retried”.
If the comparison is successful, an ACK is issued back to the transmitter and the packet
is forwarded for decoding by the receiver’s Transaction layer. Typically, as each packet
is successfully received by the Data Link layer, the receiver issues an ACK. However,
the PCI Express* protocol allows that ACKs can be combined.
• Sequence number assignment for each packet
• ACK/NAK protocol to ensure successful transmission of every packet
• CRC protection of packets
• Timeout mechanism to detect “lost” packets
• Credit exchange
®
5100 MCH Chipset
Seq #
DLLP
TLP
Intel
illustrates the scope of the link
®
5100 Memory Controller Hub Chipset
CRC
Datasheet
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