HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 183

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.13.24
3.8.13.25
3.9
3.9.1
3.9.1.1
July 2009
Order Number: 318378-005US
ERR0_INT - Internal Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits
MCERR_INT - Internal MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT,
and MCERR_INT for each of the corresponding bits
Memory Control Registers
General Registers
MC - Memory Control Settings
Miscellaneous controls not implemented in other registers.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Bit
31
7:5
7:5
Bit
Bit
4
3
2
1
0
4
3
2
1
0
Attr
RV
®
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
5100 MCH Chipset
RV
RV
RV
RV
16
2
D0h
16
2
D3h
16
1
40h
Default
0
Default
Default
7h
7h
1
1
1
1
1
1
1
1
1
1
Reserved
Reserved
B5McErrMsk: Address Map Error
B4McErrMsk: SMBus Virtual Pin Error
B3McErrMsk: Coherency Violation Error for EWB
Reserved
B1McErrMsk: DM Parity Error
Reserved
B5Err0Msk: Address Map Error
B4Err0Msk: SMBus Virtual Pin Error
B3Err0Msk: Coherency Violation Error for EWB
Reserved
B1Err0Msk: DM Parity Error
Description
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
183