HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 126

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.29
Intel
Datasheet
126
®
5100 Memory Controller Hub Chipset
PEXLWSTPCTRL: PCI Express* Link Width Strap Control Register
This register provides the ability to change the PCI Express* link width through
software control. Normally, the Intel
pins to train the links. However, if BIOS needs the ability to circumvent the pin
strappings and enforce a specific setting for a given platform, it must perform a soft
initialization sequence through the following actions in this register:
The chipset will then use the values initialized in the PEXLWSTPCTRL.GPMNXT0(1)
fields and train the links appropriately following the hard reset. The Intel
Chipset will also provide status information to the software as to what link width it is
currently using to train the link via PEXLWSTPCTRL.GPMCUR0(1) fields and the
appropriate training mode, PEXLWSTPCTRL.LWTM. (pins strap vs. software enabled
mode)
Device:
Function:
Offset:
Device:
Function:
Offset:
15:14
1. Set PEXLWSTPCTRL.LWOEN to ‘1’.
2. Write the desired link width to PEXLWSTPCTRL.GPMNXT0(1) fields for IOU0 and
3. Perform a hard reset to the Intel
Bit
Bit
2
1
0
IOU1 clusters.
RV
Attr
Attr
RW
RW
RW
7-2
0
3Eh
0
0
40h
0h
Default
Default
0
0
0
Reserved
ISAEN: ISA Enable
Modifies the response by the Intel
by the CPU that target ISA I/O addresses. This applies only to I/O addresses
that are enabled by the IOBASE and IOLIM registers.
1: The Intel
transactions addressing the last 768 bytes in each 1 kB block even if the
addresses are within the range defined by the IOBASE and IOLIM registers.
See
these cycles will be forwarded to ESI where they can be subtractively or
positively claimed by the ISA bridge.
0: All addresses defined by the IOBASE and IOLIM for CPU I/O transactions
will be mapped to PCI Express*.
BCSERRE: SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express* port to the primary side.
1: Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages.
0: Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL.
Note that BCSERRE is no longer a gating item for the recording of the
SESCSTS.SRSE error.
PRSPEN: Parity Error Response Enable
This bit controls the response to poisoned TLPs in the PCI Express* port
1: Enables reporting of poisoned TLP errors.
0: Disables reporting of poisoned TLP errors
Section 4.5.2, “Outbound I/O Access.”
®
®
®
5100 MCH Chipset will not forward to PCI Express* any I/O
5100 MCH Chipset will use the PEWIDTH[3:0]
5100 MCH Chipset.
Intel
Description
®
Description
®
5100 MCH Chipset—Register Description
5100 MCH Chipset to an I/O access issued
Instead of going to PCI Express*
Order Number: 318378-005US
®
5100 MCH
July 2009