HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 181

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.13.19
3.8.13.20
3.8.13.21
July 2009
Order Number: 318378-005US
NERR_NF_INT - Internal Next Non-Fatal Error Register
NRECINT - Non Recoverable Internal Intel
Hub Chipset Error Log Register
This register will log non-recoverable errors (Fatal and Non Fatal) based on the internal
MCH errors that originate from the FERR_FAT_INT, FERR_NF_INT described starting
from
debugging VPP errors in this register, e.g., if VPP_PEX_PORT2-3 is set, then software
can scan the PCI Express* configuration space for unit errors logged in the device 2, 3
for PEX_UNIT_FERR/NERR register as defined in
“PEX_UNIT_FERR[7:2] - PCI Express* First Unit Error Register”
port.
EMASK_INT - Internal Error Mask Register
A ‘0’ in any bit position enables the corresponding error.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:21
20:13
12:11
10:8
7:1
6:0
Bit
Bit
Bit
0
0
7
Section 3.8.13.16, “FERR_FAT_INT - Internal First Fatal Error Register.”
®
RWCST
RWCST
ROST
ROST
ROST
Attr
Attr
Attr
RV
RV
RV
5100 MCH Chipset
RV
16
2
C2h
16
2
C3h
16
2
C4h
Default
Default
Default
000
0h
0h
00
0h
0
0h
0
0
Reserved
DM (Data Manager) entry
Reserved
Internal Block that detected the Failure
000: Default no errors detected
001: VPP_PEX_PORT2-3
010: VPP_PEX_PORT4-7
011: VPP_MEM
100: COH
101: DM
Others: Reserved
Reserved
COH Entry of Failed Location
Reserved
B5Err: Address Map Error (COH)
B1Err: DM Parity Error (DM)
Section 3.8.12.28,
Description
®
Description
Description
Intel
5100 Memory Controller
®
5100 Memory Controller Hub Chipset
to determine the failing
For
Datasheet
181