HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 237

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.21.4
3.11.21.5
3.11.21.6
3.11.21.7
July 2009
Order Number: 318378-005US
FERR_CHANSTS - First Error Channel Status Register
FERR_DESC_CTRL - First Error Descriptor Control Register
This register contains the desc_ctrl fields extracted from the current descriptor when an
error happened.
FERR_SADDR - First Error Source Address Register
This register records the source address of the current descriptor which encountered an
error.
FERR_DADDR - First Error Destination Address Register
This register records the destination address of the current descriptor which
encountered an error.
Device:
Function:
Offset:
63:6
5
4:3
2:0
Device:
Function:
Offset:
31:0
Device:
Function:
Offset:
63:0
Bit
Bit
Bit
RWCST
RV
RWCST
RWCST
RWCST
RWCST
Attr
Attr
Attr
®
5100 MCH Chipset
8
0
84h
8
0
8Ch
8
0
90h
0h
0
00
011
0h
0h
Default
Default
Default
FERR_Completed Descriptor Address: This register stores the upper address
bits of the current DMA descriptor (CHAINADDR) when an error is encountered.
Reserved
FERR_DMA Channel number: This field records the Channel number of the
DMA Engine that encountered an error.
FERR_DMA Transfer Status: The DMA Engine sets the bits indicating the state
of the current DMA transfer when an error is encountered.
000 - Active
001 - Completed, DMA Transfer Done (no hard errors)
010 - Suspended
011 - Halted, operation aborted (refer to Channel Error register for further detail)
FERR_Desc_ctrl: This field records the “desc_ctrl” field from the current
descriptor that encountered an error.
FERR_Source Address: This 64 bit field marks the address of the source
address in a given descriptor that encountered an error.
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
237