HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 131

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.32
July 2009
Order Number: 318378-005US
This 32-bit register implements chipset specific operations for general control/
accessibility such as device hiding, selective configuration cycles and interrupt signaling
PEXCTRL2[7:2,0]: PCI Express* Control Register 2
This is an auxiliary control register for PCI Express* port specific debug/defeature
operations.
Device:
Function:
Offset:
Device:
Function:
Offset:
6:3
Bit
7:1
Bit
2
1
0
0
2) {RWO}
if (port 7-
elsif (port
®
Attr
0) {RV}
RW
RV
endif
5100 MCH Chipset
Attr
RW
RW
RW
7-2,0
0
48h
7-2, 0
0
4Ch
Default
00h
0
Default
0000
1
0
0
Reserved
NO_COMPLIANCE:
Set by software to enable link operation in the presence of single wire failures
on the link. If clear, then specified link behavior in the presence of a wire
failure will be Polling.Compliance.
VPP: Virtual Pin Port
[6:4] = SMBus Address, [3] = I/O Port
defines the 8-bit I/O port that is used for routing power, attention, PCI
Hot Plug*, presence, MRL and other events defined in
“PEXSLOTCTRL[7:2, 0] - PCI Express* Slot Control Register.”
DIS_VPP: Disable VPP
The Intel
is valid or not for the given PCI Express* port as set by configuration
software. For example, to distinguish HP events for a legacy card or PCI
Express* port module, this bit can be used.
1: VPP is disabled for this PCI Express* port.
0: VPP is enabled for this PCI Express* port.
Default value is to disable vpp for the PCI Express* port
DIS_APIC_EOI: Disable APIC EOI
The Intel
interrupts (EOI) need to be sent to an APIC controller/bridge (e.g., Intel
6700PXH 64-bit PCI Hub) through this PCI Express* device.
1: no EOIs are sent (disabled).
0: EOIs are dispatched to the APIC Controller.
Note:
DEVHIDE: Device_hide
The device hide bit is used to enable the Intel
the PCI Express* device from the Operating system and is applicable only
to ports 7-2. Typically, an external I/O processor acts as its proxy by
configuring it and claiming resources on behalf of it and then unhides.
The hiding is done by changing the class code (CCR register) for this port
to 0600h. This will prevent the OS from attempting to probe or modify
anything related to this device.
1: The PCI Express* port CCR register has a value of 0600.
0: The PCI Express* port CCR register has a value of 0604 (bridge)
The default value is ‘0’ (to make the device a bridge).
The device hide bit does not apply to the ESI interface (port 0) and has
no effect on its operation
The Intel
to unconnected ports (hanging) or to slave ports (secondary). In
general, EOI should be disabled for active ports that have a non-
I/O APIC controller attached to them for performance
considerations.
®
®
5100 MCH Chipset will use this bit to decide whether the VPP
5100 MCH Chipset will use this bit to decide whether end of
®
5100 MCH Chipset will block the EOIs from being sent
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset to hide
Section 3.8.11.10,
Datasheet
®
131