HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 381

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics—Intel
6.2.2
Table 127.
6.2.3
Table 128.
July 2009
Order Number: 318378-005US
V
V
V
V
I
I
I
R
GTLREF
R
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Single-ended Signals
V
V
V
V
I
I
Notes:
1.
2.
3.
OL
LI
LO
OH(dc)
OL(dc)
IL
IH
OL
OH
on
TT
IN
IH(dc)
IL(dc)
OTR
Symbol
Symbol
GTLREF is equivalent to FSB{0/1}VREF. GTLREF is generated from V
resistors.
V
V
V
“Overshoot/Undershoot Tables”
Specification (EDS) Addendum.
Leakage to Vss with land held at V
Leakage to V
Use 50 Ω±15% for all microstrip.
I
(Voltage Regulator). Half of the total current goes through R
the CPU (the end-bus-agency).
Input voltage for all pins is limited to a maximum of 2.3 V.
VCCDDR/2=1.7/2=850 mV
C
OL
IL
IH
IH
IO
is defined as current when the output is low. The formula computes the total current drawn by the driver from the Vr
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
and V
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
is the input/output capacitance for DQ/DQS and output capacitance for CMD/ADDR/CLK.
Front Side Bus (FSB) Interface
FSB DC Characteristics
DDR2 Interface
DDR2 DC Characteristics (Sheet 1 of 2)
OH
may experience excursions above V
TT
Host AGTL+ Input Low Voltage
Host AGTL+ Input High Voltage
Host AGTL+ Output Low Voltage
Host AGTL+ Output High Voltage
Host AGTL+ Output Low Current
Host AGTL+ Input Leakage
Current
Host AGTL+ Output Leakage
Current
Buffer on Resistance
Host Bus Reference Voltage
Host Termination Resistance
Common Clock, Async on
Stripline
Input Voltage
DC High-level Input Voltage
DC Low-level Input Voltage
Output Timing Measurement
Reference Level
Output Minimum Source DC
Current
Output Minimum Sink DC
Current
with land held at 300 mV
®
Parameter
Parameter
5100 MCH Chipset
of the Intel
TT
®
5100 Memory Controller Hub Chipset (embedded) – External Design
CC.
GTLREF+(0.1xV
However, input signal drivers must comply with
(0.98x0.67)xV
VCCDDR/2+100
0.90xV
-13.8
Min.
Min.
-300
13.8
N/A
N/A
45
0
7
0
-
TT
TT
on the chipset, and another half goes through the R
TT
TT
)
TT
on the baseboard by a voltage divider of 1%
0.67xV
VCCDDR
Nom.
Nom.
0.5x
50
-
-
-
-
-
Intel
TT
®
5100 Memory Controller Hub Chipset
GTLREF-(0.1xV
R
(1.02x0.67)xV
VCCDDR/2-100
VCCDDR+300
tt_min
V
TT
± 200
± 200
Max.
Max.
/(0.50x
V
V
0.4
V
+R
11
55
DD
-
-
-
TT
TT
on_min
Section 5.0,
TT
TT
)
)
Unit
Unit
mA
mV
mV
mA
mA
µA
µA
Ω
Ω
V
V
V
V
V
V
Datasheet
Notes
Notes
TT
1,
1,
5,
5,
4
8
1
7
2
2
on
2
3
6
6
381