HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 224

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.5
3.11.6
3.11.7
3.11.8
Intel
Datasheet
224
®
5100 Memory Controller Hub Chipset
CAPPTR: Capability Pointer Register
INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver
not have a dedicated interrupt line and is not used
INTP: Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
Assert_INTx commands as appropriate.
DMACTRL: DMA Control Register
This 32-bit register implements DMA specific operations for general control/accessibility
such as defeaturing, arbitration.
Device:
Function:
Offset:
7:0
Device:
Function:
Offset:
Device:
Function:
Offset:
Bit
7:0
7:0
Bit
Bit
RO
Attr
RWO
RWO
Attr
Attr
8
0
34h
8
0
3Ch
8
0
3Dh
50h
Default
Default
Default
00h
01h
CAPPTR: Capability Pointer
This register field points to the first capability. PM structure in the DMA Engine
device.
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which
input of the interrupt controller this PCI Express* Port is connected to. Not
used in the Intel
have interrupt lines.
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express* port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
®
5100 MCH Chipset since the PCI Express* port does not
Intel
.
Description
The Intel
®
.
Description
Description
5100 MCH Chipset—Register Description
®
5100 MCH Chipset does
Order Number: 318378-005US
July 2009