HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 406

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 143.
Intel
Datasheet
406
Ball No.
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T1
T2
T3
T4
T5
T6
T7
T8
T9
®
5100 Memory Controller Hub Chipset
CH1_DQSN[17]
CH1_DQSP[4]
CH0_DQSP[5]
CH0_DQSN[5]
Signal Name
Intel
CH1_DQ[36]
CH1_DQ[45]
CH1_DQ[40]
CH0_DQ[46]
CH1_CB[1]
PE2TN[3]
PE2TN[1]
PE2TN[0]
PE2RP[3]
PE2RP[0]
PE2TP[0]
VCCDDR
VCCPE
VCCPE
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
®
5100 Memory Controller Hub Chipset Signals By Ball (Sheet 7 of 16)
Buffer Type Direction Ball No.
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
PEX
PEX
PEX
PEX
PEX
PEX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
Intel
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
®
U1
U2
U3
U4
U5
U6
U7
U8
U9
5100 MCH Chipset—Ballout and Package Information
CH1_DQSP[17]
CH1_DQSN[8]
Signal Name
CH1_DQ[47]
CH1_DQ[46]
CH0_DQ[47]
CH0_DQ[42]
CH0_DQ[43]
CH1_CB[0]
CH1_CB[7]
CH1_CB[2]
CH1_CB[5]
PE2RN[3]
PE3RN[3]
PE3TN[2]
PE3TP[0]
PE2TP[1]
PE3TP[2]
PE3RP[3]
VCCDDR
VCCDDR
VCCDDR
VCCPE
VCCPE
VCCPE
VCCPE
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
Order Number: 318378-005US
Buffer Type Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
PEX
PEX
PEX
PEX
PEX
PEX
PEX
July 2009
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I