HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 179

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.13.14
3.8.13.15
July 2009
Order Number: 318378-005US
ERR0_FSB[1:0]: FSB Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
MCERR_FSB[1:0]: FSB MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:9
15:9
15:9
4:2
4:2
Bit
Bit
Bit
8
7
6
5
1
0
8
7
6
5
1
0
8
7
6
®
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
5100 MCH Chipset
Attr
RV
RV
RV
RV
RV
16
0
496h, 196h
16
0
494h, 194h
16
0
49Ah, 19Ah
Default
Default
Default
0h
0h
0h
1
1
1
1
1
1
1
1
1
0h
0h
1
1
1
1
1
1
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Description
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
179