HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 241

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.22.2
3.11.22.3
3.11.22.4
July 2009
Order Number: 318378-005US
XFERCAP - Transfer Capacity
The Transfer Capacity specifies the minimum of the maximum DMA transfer size
supported on all channels.
INTRCTRL - Interrupt Control
The Interrupt Control register provides for control of DMA interrupts.
ATTNSTATUS - Attention Status
The Interrupt Status register identifies which channels have generated an interrupt and
provides the means for the interrupt service routine to reset the interrupt. This register
works in conjunction with the Interrupt Disable bit in the CHANCTRL register of the per-
channel registers. (See
Offset:
7:5
4:0
Offset:
7:3
2
1
0
Offset:
31:4
Bit
Bit
Bit
RV
RO
RV
RO
RO
RW
RV
Attr
Attr
Attr
®
5100 MCH Chipset
01h
03h
04h
0h
01100
0h
0
0
0
0h
Default
Default
Default
Reserved
Trans_cap: Transfer Capacity
This field specifies the number of bits that may be specified in a DMA descriptor’s
Transfer Size field. This defines the minimum of the maximum transfer size
supported by Intel
01100: The value of 12 indicates 4 kB maximum transfer in Intel
Chipset and is the default value
Others: Reserved
Reserved
intp: Interrupt
This bit is set whenever any bit in the Attention Status register is set and the
Master Interrupt Enable bit is set. That is, it is the logical AND of Interrupt Status
and Master Interrupt Enable bits of this register. This bit represents the legacy
interrupt drive signal (when in legacy interrupt mode) and for MSI mode, the
hardware sends an MSI interrupt each time this signal transitions from reset to set.
intp_sts: Interrupt Status
This bit is set whenever any bit in the Attention Status register is set. That is, it is
the logical OR of the Channel Attention bits of the ATTNSTATUS register.
Mstr_intp_En: Master Interrupt Enable
Setting this bits enables the generation of an interrupt. This bit is automatically
reset each time this register is read. When this bit is clear, the chipset will not
generate an interrupt (i.e., does not send MSI nor drive the legacy interrupt signal).
Reserved
Section
3.11.23.2.
®
5100 MCH Chipset as a power of 2.
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
241