HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 69

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Figure 9.
July 2009
Order Number: 318378-005US
Conceptual Intel
Diagram
12 USB Ports,
6 SATA, 3 Gb
Controllers
PCI Express*
PCI Express*
PCI Express*
PCI Express*
2 EHCI
Port 4
Port 5
Port 6
Port 7
x4
x4
x4
x4
®
5100 MCH Chipset
Intel® 5100 MCH
Chipset
®
Bus 0, Dev 16, Func 2-0
FSB Interrupt, System
Bus 0, Dev 29, Func 0-3
Bus 0, Dev 26, Func 0-1
Controller, Error Reg
Bus 0, Dev 29, Func 7
Bus 0, Dev 31, Func 2
5100 Memory Controller Hub Chipset PCI Configuration
Bus 0, Dev 26, Func 7
Bus 0, Dev 31, Func 5
PCI Express* Port 4
Bridge Bus 0, Dev 4
PCI Express* Port 5
Bridge Bus 0, Dev 5
PCI Express* Port 6
Bridge Bus 0, Dev 6
PCI Express* Port 7
Bridge Bus 0, Dev 7
Address, Memory
USB1.1 Controllers,
SATA Controller 1,
Bus 0, Dev 25, Func 0
USB2 Controller 1,
USB2 Controller 2,
SATA Controller 2,
LAN Controller
Processor 0
10/100/1000
PCI Config Window in I/O Space
(PCI Express* Bridge
(PCI Express* Bridge
Bus 0, Dev 30)
Bus 0, Dev 0)
ESI
ESI
ESI Interface (logical PCI Bus 0)
Mask, Channel Control for
Mask, Channel Control for
Memory Map, Error Flag/
Memory Map, Error Flag/
Bus 0, Dev 28 Func 0-5
Bus 0, Dev 31, Func 3
Bus 0, Dev 31, Func 6
Bus 0, Dev 21, Func 0
Bus 0, Dev 22, Func 0
Bus 0, Dev 31, Func 0
Thermal Subsystem
HD Audio Controller
PCI Express* Port 2
Bridge Bus 0, Dev 2
PCI Express* Port 3
Bridge Bus 0, Dev 3
Bus 0, Dev 27, Func 0
PCI Express* Ports
SMBus Controller
Processor 1
DMA Controller
PCI-LPC Bridge
Bus 0, Dev 8
Channel 0
Channel 1
Intel
®
5100 Memory Controller Hub Chipset
ICH9R
PCI Express*
LPC Bus
Root Ports
PCI Express*
PCI Express*
0310071328
6 x1
Port 3
Port 2
x4
x4
Datasheet
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