HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 207

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 67.
3.9.6.13
3.9.6.14
July 2009
Order Number: 318378-005US
ECC Locator Mapping Information (Sheet 2 of 2)
RECMEMA[1:0]: Recoverable Memory Error Log Register A
This register latches information on the first detected non-fatal memory error. An
uncorrectable ECC error is non-fatal.
RECMEMB[1:0]: Recoverable Memory Error Log Register B
This register latches information on the first detected non-fatal memory error. An
uncorrectable ECC error is non-fatal
Device:
Function:
Offset:
Device:
Function:
Offset:
31:20
19:15
14:12
30:29
28:16
10:8
15:0
7:0
Bit
Bit
11
31
DS[17:16]
DS[19:18]
DS[21:20]
DS[23:22]
DS[25:24]
DS[27:26]
DS[29:28]
DS[31:30]
Symbols
CS[1:0]
CS[3:2]
®
ROST
ROST
ROST
ROST
ROST
ROST
ROST
Attr
Attr
RV
RV
RV
5100 MCH Chipset
22, 21
0
1A0h
22, 21
0
1A4h
Default
Default
000h
000
00h
0h
0h
00
0h
0
0
0
Reserved
MERR: identifies error that triggered the RECMEM and REDMEM logs
BANK: Bank of the failed request
Reserved
RANK: Rank of the failed request
DM_BUF_ID: DM Buffer ID of the failed request
RDWR: should always be 0
‘0’ = Read
‘1’ = Write
Reserved
CAS: CAS address of the failed request
The CAS address will map from 12:0 while bit 10 (autoprecharge) is
hardwired to 0.
RAS: RAS address of the failed request
DQS Lane
DQS10
DQS11
DQS12
DQS13
DQS14
DQS15
DQS16
DQS17
DQS8
DQS9
DQ[67:64]
DQ[15:12]
DQ[23:20]
DQ[31:28]
DQ[39:36]
DQ[47:44]
DQ[55:52]
DQ[63:60]
DQ[71:68]
DQ Lane
DQ[7:4]
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Locator Bit
10
11
12
13
14
15
16
17
8
9
Datasheet
207