HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 345

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.19.1.5
5.19.2
Figure 34.
July 2009
Order Number: 318378-005US
BINIT# Mechanism
The BINIT# mechanism is provided to facilitate processor handling of system errors
which result in a hang on the FSB. The Machine Check Architecture (MCA) code
responding to an error indication, typically IERR# or MCERR#, will cause an attempt to
interrogate the MCH for error status, and if that FSB transaction fails to complete the
processor will automatically time out and respond by issuing a BINIT# sequence on the
FSB.
When BINIT# is asserted on the FSB, all bus agents (CPUs and MCH) are required to
reset their internal FSB arbiters and all FSB tracking state machines and logic to their
default states. This will effectively “un-hang” the bus to provide a path into chipset
configuration space. Note that the MCH device implements “sticky” error status bits,
providing the platform software architect with free choice between BINIT# and a
general hard reset to recover from a hung system.
Although BINIT# will not clear any configuration status from the system, it is not a
recoverable event from which the platform may continue normal execution without first
running a hard reset cycle. To guarantee that the FSB is cleared of any hang condition,
the MCH will clear all pending transaction states within its internal buffers. This applies
to outstanding FSB cycles as required, but also to in-flight memory transactions and
inbound transactions. The resulting state of the platform will be highly variable
depending upon what precisely got wiped-out due to the BINIT# event, and it is not
possible for hardware to guarantee that the resulting state of the machine will support
continued operation. What the MCH will guarantee is that no subordinate device has
been reset due to this event (PCI Express* links will remain “up”), and that no internal
configuration state (sticky or otherwise) has been lost. The MCH will also continue to
maintain main memory via the refresh mechanism through a BINIT# event, thus
machine-check software will have access not only to machine state, but also to
memory state in tracking-down the source of the error.
Intel
General power sequencing requirements for the Intel
In general higher voltages must come up before lower voltages.
5100 Memory Controller Hub Chipset Power Sequencing”
four main voltages powering the Intel
Intel
Note:
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Power-up -> 3.3 V must ramp ahead and stay above 1.8 V, which must ramp ahead and stay above
1.5 V which must ramp and stay above 1.2 V (VTT). 3.3 V must always be at least 0.7 V greater than
1.5 V. Duration of the power ramp of each individual supply must be between 0.1 ms and 100 ms. The
power down sequence is not as critical. When transiting to power down states, 1.8 V may stay up as
required while the other supplies decay to 0 V as needed. See the Quad-Core and Dual-Core Intel
Xeon
Communications, Embedded, and Storage Applications – Platform Design Guide or Intel
Processors T9400 and SL9400 and Intel
and Embedded Applications – Platform Design Guide for the most current information.
5100 Memory Controller Hub Chipset Power Sequencing
5100 Memory Controller Hub Chipset Power Sequencing
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5100 MCH Chipset
Processor 5000 Sequence with Intel
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5100 Memory Controller Hub Chipset for Communications
5100 MCH Chipset.
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5100 Memory Controller Hub Chipset for
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Intel
5100 MCH Chipset are simple.
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depicts the sequencing of the
5100 Memory Controller Hub Chipset
Figure 34, “Intel®
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Core™2 Duo
Datasheet
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