HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 364

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 117.
5.21
Intel
Datasheet
364
®
5100 Memory Controller Hub Chipset
For the maximum number of six I/O Ports, and assuming no clock stretching, this
sequence can take up to 51 ms. If new PCI Hot Plug* capability bits are not being set,
this is the maximum timing uncertainty in sampling or driving these signals.
Table 117
PCI Hot Plug* Signals on Virtual Pin Port
The Intel
Deassert_HPGPE messages to the ESI port as virtual pin messages to enable the ICH9R
take the appropriate action for handling the PCI Hot Plug* (legacy/ACPI interrupt
mode) in non-MSI mode.
Trusted Platform Module (TPM)
The Intel
system. TPM locality 0 access is mapped to FED4_0xxxh MMIO address range. With
TPM, the Intel
is accessed through address space FED4_0xxxh. The Intel
open FED4_0xxxh - FED4_0FFFh to processors in the system. It is available at all times
and is capable of being accessed by all processors. The Intel
convert these CPU accesses into corresponding Read/Write messages on the ESI port
and send it to Intel
Only the Memory Read is non-posted and requires a completion. However, Memory
Writes are posted. The completion for the Memory Read will be the same as for normal
read completion cycles. If a zero length read/write is targeted to FED4_0xxxh space,
the Intel
send the request south through the ESI port.
The Intel
they will be routed to the ESI port as standard Memory transactions. The same rule
also applies to Peer-to-peer accesses for locality 1-4 accesses.
Locked accesses to FED4_0xxxh range are not supported and will be master aborted by
the Intel
internal master abort mechanism, it will be passed as MMIO transactions to ESI. All
peer-to-peer requests that attempt to access the TPM space will be allowed as normal
memory transactions on the ESI port (i.e., it will not be converted to Read/Write). Refer
to
to the originating port in the Intel
Bit
0
1
2
3
4
5
6
7
Table
Direction
Output
Output
Output
Input
Input
Input
Input
Input
®
®
118. Such a peer-to-peer transaction will be master aborted by the ICH9R port
®
®
®
describes the PCI Hot Plug* Signals used for PCI Hot Plug*.
5100 MCH Chipset has the ability to either complete the request internally or
5100 MCH Chipset. Since the Intel
5100 MCH Chipset will send Assert_INTx/Deassert_INTx or Assert_HPGPE/
5100 MCH Chipset supports TPM v1.2 locality 0 access from CPU on the
5100 MCH Chipset will decode TPM locality 1-4 addresses on the FSB and
®
5100 MCH Chipset allows security to exist within the platform. The TPM
Logic Level
High_true
High_true
High_true
High_true
Low_true
Low_true
Low_true
Low_true
Voltage
®
82801IR I/O Controller Hub.
BUTTON#
PWRFLT#
PWRLED
PRSNT#
ATNLED
PWREN
Signal
GPI#
MRL
®
5100 MCH Chipset.
ATTN LED is to be turned ON ATTN LED is to be turned OFF
PWR LED is to be turned ON
Power is to be enabled on
ATTN Button is Pressed
Logic True Meaning
PWR Fault in the VRM
Card Present in Slot
Power good on Slot
Intel
®
MRL is open
5100 MCH Chipset does not have an
the Slot
®
5100 MCH Chipset—Functional Description
®
5100 MCH Chipset will only
®
5100 MCH Chipset will
Order Number: 318378-005US
PWR LED is to be turned OFF
ATTN Button is NOT Pressed
Power is NOT to be enabled
No PWR Fault in the VRM
Card NOT Present in Slot
No Power good on Slot
Logic False Meaning
MRL is closed
on the Slot
July 2009