HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 191

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.9.2.4
3.9.3
3.9.3.1
July 2009
Order Number: 318378-005US
THRTLOW: Thermal Throttle Low Register
The two thermal throttle registers set the limit for activations to a given rank during a
thermal throttle activation window (1344 cycles). Should the limit (“HIGH” or “LOW” as
selected by GBLTHRT) be exceeded then further activations will be prevented for the
duration of the window.
Memory Gearing Registers
DDRFRQ: DDR Frequency Ratio
This register specifies the CORE:DDR frequency ratio. The “other”
“MEMTOHOSTGRCFG0: MEM to Host Gear Ratio Configuration 0”
3.9.3.7, “HOSTTOMEMGRCFG1: Host to MEM Gear Ratio Configuration
configuration registers must be set prior to changing the “DDRFRQ” field of this
register. This register must be written once after a hard reset.
Device:
Function:
Offset:
Device:
Function:
Offset:
7:0
7:6
5:4
Bit
Bit
3
RWST
ROST
Attr
Attr
RW
RV
®
5100 MCH Chipset
16
1
64h
16
1
56h
Default
Default
0h
01
0
1
THRTLOWLM: Thermal Throttle Low Limit
A base throttling level that is applied when the THRTSTS.GBLTHRT* bit is not set by
the Global Throttling Window logic.
Note:
The maximum value this field can be initialized by software is 168 (decimal). This
corresponds to 672 activations per throttling window and gives 100% BW.
The granularity of this field is 4 activations.
0: No throttling (unlimited activation)
1: 4 activations per rank per activation window
2: 8 activations per rank per activation window
168: 672 activations per rank per activation window
If Software sets this value greater than 168, the chipset will cap the THRTLOWLM
field to 168.
Reserved
CURDDRFRQ: CORE:DDR Frequency Ratio (current ratio)
‘00’ = 1:1. BUSCLK=266 MHz, DDR=533 MHz.
‘01’ = 1:1. BUSCLK=333 MHz, DDR=667 MHz.
‘10’ = 4:5. BUSCLK=266 MHz, DDR=667 MHz.
‘11’ = 5:4. BUSCLK=333 MHz, DDR=533 MHz.
COREFREQ: CORE Frequency
This frequency ratio tells the SPD master which divider ratio to employ in order to
operate at 100 kHz.
‘1’ = Core is operating at 333 MHz. SPD Divider ratio = 3,334
‘0’ = Core is operating at 266 MHz. SPD Divider ratio = 2,667
BIOS programming is optional. If BIOS doesn’t program this bit, then if the core is
operating at 266 MHz, the SPD link will operate at 80 kHz.
The GBLTHRT* is an internal signal from the Intel
open loop combinatorial cluster before it is latched in the THRTSTS.GLTHRT
register. This will prevent any stale/delayed information from being used
for the open loop throttling logic.
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
through
(Section 3.9.3.2,
®
5100 MCH Chipset
1”) gearing
Section
Datasheet
191