HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 339

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.5
5.17.5.1
5.17.5.1.1
July 2009
Order Number: 318378-005US
Ordering Rules
This section describes the MCH ordering rules for transactions progressing through the
PCI Express* unit.
Inbound Transaction Ordering Rules
Inbound transactions originate from PCI Express* and target main memory. In general,
the PCI Express* cluster holds inbound transactions in FIFO order. There are exceptions
to this order under certain situations. For example, PCI Express* requires that read
completions are allowed to pass read requests. This forces any read completions to
bypass any reads which might be back pressured in the queue. The PCI Express* ports
have no ordering relationship to each other (aside from the peer-to-peer restrictions
below).
Sequential non-posted requests are not required to be completed in the order they
were requested. However, if a non-posted request requires multiple sub-completions
(typically due to splitting a memory read into cache line requests), then those sub-
completions must be delivered in order.
Inbound writes cannot be posted beyond the PCI Express* domain and outbound writes
may only be posted after the write is acknowledged by the destination PCI Express*
cluster. The posting of writes relies on the fact that the system maintains a certain
ordering relationship. Since the MCH cannot post inbound writes beyond the PCI
Express* cluster, the MCH must wait for snoop responses before issuing subsequent,
order-dependent transactions.
Inbound Ordering Requirements
In general, there are no ordering requirements between transactions issued on the
different PCI Express* interfaces. The following rules apply to inbound transactions
issued on the same interface.
The following rules must be ensured for inbound transactions:
RULE 1: Outbound non-posted read and write completions must be allowed to
RULE 2: Inbound posted write requests must be allowed to progress past stalled
RULE 3: Inbound posted write requests, inbound read requests, outbound non-posted
The Producer - Consumer model prevents read requests, write requests, and non-
posted read or write completions from passing write requests. Refer to PCI Local Bus
Specification, Rev. 2.3 for details on the Producer - Consumer ordering model.
RULE 4: Outbound non-posted read or write completions must push ahead all prior
RULE 5: To optimize performance, Inbound, coherent, posted writes will issue
RULE 6: Inbound messages follow the same ordering rules as inbound posted writes.
Inbound messages are listed in
to inbound posted writes, reads should push these commands ahead.
progress past stalled inbound non-posted requests.
inbound non-posted requests.
read and write completions cannot pass enqueued inbound posted write
requests.
inbound posted write transactions from that PCI Express* port.
ownership requests (RFO) without waiting for prior ownership requests to
complete.
®
5100 MCH Chipset
Table 102, “Incoming PCI Express*
Intel
®
5100 Memory Controller Hub Chipset
Requests”. Similarly
Datasheet
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