HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 208

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.7
3.9.7.1
3.9.7.2
Intel
Datasheet
208
®
5100 Memory Controller Hub Chipset
Sparing Registers
There are one set of registers for the single memory channel. The registers appear in
function 0 of different devices as shown in
Intel® 5100 Memory Controller Hub Chipset.”
SPCPC[1:0]: Spare Copy Control
These controls set up sparing for each channel. Channel zero (device 21) takes
precedence over channel one (device 22): if both spare-control-enabled channels’
spare error thresholds trigger in the same cycle, sparing will only commence on
channel zero. Sparing will not commence on a competing channel until it’s in-progress
competitor’s spare control enable is cleared and it’s CERRCNT criteria is still met.
SPCPS[1:0]: Spare Copy Status
Device:
Function:
Offset:
Device:
Function:
Offset:
23:19
18:16
15:8
4:3
2:0
Bit
Bit
7
6
5
7
Attr
RWL
Attr
RW
RW
RW
RW
RO
RV
RV
RV
22, 21
0
40h
22, 21
0
43h
Default
Default
0h
00
0h
0h
0h
00
0
0
0
Reserved
FORCERANK: “From” Rank for Forced Spare Copy
SETH: Spare Error Threshold
A spare fail-over operation will commence when the SPAREN bit is set and a
CERRCNT.RANK[i] count for one and only one rank hits this threshold. The SETH
field of the SPCPC registers must be programmed during initial BIOS configuration.
If the SETH field of the SPCPC registers are attempted to be re-programmed after
initial BIOS configuration with a value smaller than the current value of
CERRCNT.RANK[i], sparing will not occur.
Reserved
FORCE: Initiate Spare Copy
‘0’~>’1’ transition while SPCPS.DSCIP = 0 initiates spare copy.
SPAREN: Spare Control Enable
‘1’ enables sparing, ‘0’ disables sparing. The SPRANK field defines other
characteristics of the sparing operation.
If this bit is cleared before SPCPS.SFO is set, then if this bit is subsequently set
while the spare trigger is still valid, then the spare copy operation will not resume
from where it left off, but will instead restart from the beginning.
Reserved
SPRANK: Spare Rank
Target of the spare copy operation. This rank should not initially appear in a
DMIR.RANK field. After the spare copy, the device will update the failed DMIR.RANK
fields with this value. Enabled by SPAREN. Changes to this register will not be
acknowledged by the hardware while SPCPS.DSCIP is set.
LBTHR: Leaky Bucket Threshold Reached
‘0’ = Leaky-bucket threshold not reached
‘1’ = Leaky-bucket count matches SPCPC.SETH. Generates error M20. Cleared by
reducing the offending count(s) in the CERRCNT registers.
Table 28, “Functions Specially Handled by
Intel
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009