HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 245

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.23.2
3.11.23.3
July 2009
Order Number: 318378-005US
CHANCTRL[3:0] - Channel Control Register
The Channel Control register controls the behavior of the DMA channel when specific
events occur such as completion or errors.
CHANSTS[3:0]: Channel Status Register
Offset:
15:9
8
7:6
5
4
3
2
1
0
Offset:
63:6
Bit
Bit
RV
RW
RV
RW
RW
RW
RW
RV
RWC
RO
Attr
Attr
®
5100 MCH Chipset
200h, 180h, 100h, 80h
204h, 184h, 104h, 84h
0h
0
00
0
0
0
0
0
0
0h
Default
Default
Reserved
In_use: In Use
This bit indicates whether the DMA channel is in use. The first time this bit is read
after it has been cleared, it will return ‘0’ and automatically transition from ‘0’ to ‘1’,
reserving the channel for the first consumer that reads this register. All subsequent
reads will return ‘1’ indicating that the channel is in use. This bit is cleared by
writing a ‘0’ value, thus releasing the channel. A consumer uses this mechanism to
atomically claim exclusive ownership of the DMA channel. This should be done
before attempting to program any register in the DMA channel register set.
Reserved
Desc_addr_snp_ctrl: Descriptor address snoop control
1: When set, this bit indicates that the descriptors are not in coherent space and
should not be snooped.
0: When cleared, the descriptors are in coherent space and each descriptor address
must be snooped on the chipset.
Err_Int_En: Error Interrupt Enable
This bit enables the DMA channel to generate an interrupt (MSI or legacy) when an
error occurs during the DMA transfer. If Any Error Abort Enable (see below) is not
set, then unaffiliated errors do not cause an interrupt.
AnyErr_Abrt_En: Any Error Abort Enable
This bit enables an abort operation when any error is encountered during the DMA
transfer. When the abort occurs, the DMA channel generates an interrupt and a
completion update as per the Error Interrupt Enable and Error Completion Enable
bits. When this bit is reset, only affiliated errors cause the DMA channel to abort.
It has not effect on the Intel
detected and they automatically cause the channel to abort.
Err_Cmp_En: Error Completion Enable
This bit enables a completion write to the address specified in the CHANCMP
register upon encountering an error during the DMA transfer. If Any Error Abort is
not set, then unaffiliated errors do not cause a completion write.
Reserved
Intp_Dis: Interrupt Disable
Upon completing a descriptor, if an interrupt is specified for that descriptor and this
bit is reset, then the DMA channel generates an interrupt and sets this bit. The
choice between MSI or legacy interrupt mode is determined with the MSICTRL
register. Legacy interrupts are further gated through INTxDisable bit in the PEXCMD
command register of
channel’s interrupt by writing a one to this bit, which clears the bit. Writing a zero
has no effect. Thus, each time this bit is reset, it enables the DMA channel to
generate one interrupt.
Cmp_Desc_Addr: Completed Descriptor Address
This register stores the upper address bits (64 bytes aligned) of the last descriptor
processed. The DMA channel automatically updates this register when an error or
successful completion occurs. For each completion, the DMA channel over-writes
the previous value regardless of whether that value has been read.
Section
®
3.11.1. The controlling process can re-enable this
5100 MCH Chipset since only affiliated errors are
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
245